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brushless dc motor flash type 8-bit mcu HT45FM2C revision: v1.10 date: ? a ? ? 0 ? ? 01 ? ? a ? ? 0 ? ? 01 ?
rev. 1.10 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 ? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? table of contents eates cpu features ......................................................................................................................... 7 peripheral features ................................................................................................................. 7 general description ......................................................................................... 8 block diagram .................................................................................................. 8 pin assignment ................................................................................................ 9 pin description ............................................................................................... 11 absolute ?aximum ratings .......................................................................... 14 d.c. characteristics ....................................................................................... 14 a.c. characteristics ...................................................................................... 15 a/d converter characteristics ...................................................................... 16 d/a converter characteristics ...................................................................... 16 operational amplifer characteristics clocking and pipelining ......................................................................................................... 18 program counter ................................................................................................................... 19 stack ..................................................................................................................................... ? 0 arithmetic and logic unit C alu ........................................................................................... ? 0 flash program ?emor? ................................................................................. ?1 structure ................................................................................................................................ ? 1 special vectors ..................................................................................................................... ? 1 look-up table ........................................................................................................................ ? 1 table program example ........................................................................................................ ?? in circuit programming ......................................................................................................... ?? ra? data ?emor? ......................................................................................... ?4 structure ................................................................................................................................ ? 4 special function register description ........................................................ ?6 indirect addressing registers C iar0 ? iar1 ......................................................................... ? 6 ? emor ? pointers C ? p0 ? ? p1 .............................................................................................. ? 6 bank pointer C bp ................................................................................................................. ? 7 accumulator C acc ............................................................................................................... ? 7 program counter low register C pcl .................................................................................. ? 7 look-up table registers C tblp ? tbhp ? tblh ..................................................................... ? 8 status register C status .................................................................................................... ? 8
rev. 1.10 ? ?a? ?0? ?01? rev. 1.10 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? eeprom data memory .................................................................................. 31 eepro ? data ? emor ? structure ........................................................................................ ? 1 eepro ? registers .............................................................................................................. ? 1 reading data from the eepro ? ......................................................................................... ?? writing data to the eepro ? ................................................................................................ ?? write protection ..................................................................................................................... ?? eepro ? interrupt ................................................................................................................ ?? programming consideration ................................................................................................. ?? programming examples ........................................................................................................ ? 4 oscillator ........................................................................................................ 35 oscillator overview ............................................................................................................... ? 5 system clock confgurations ................................................................................................ ? 5 internal ? 0 ? hz rc oscillator C hirc ................................................................................... ? 6 internal ?? khz oscillator C lirc ........................................................................................... ? 6 supplementar ? clocks .......................................................................................................... ? 6 operating modes and system clocks ......................................................... 37 s ? stem clocks ...................................................................................................................... ? 7 s ? stem operation ? odes ...................................................................................................... ? 9 control register .................................................................................................................... 40 fast wake-up ........................................................................................................................ 41 operating ? ode switching and wake-up .............................................................................. 4 ? nor ? al ? ode to slow ? ode switching ........................................................................... 4 ? slow ? ode to nor ? al ? ode switching ........................................................................... 4 ? entering the sleep ? ode .................................................................................................... 45 entering the idle0 ? ode ...................................................................................................... 45 entering the idle1 ? ode ...................................................................................................... 45 standb ? current considerations ........................................................................................... 46 wake-up ................................................................................................................................ 46 watchdog timer ............................................................................................. 47 watchdog timer clock source .............................................................................................. 47 watchdog timer control register ......................................................................................... 47 watchdog timer operation ................................................................................................... 48 reset and initialisation .................................................................................. 49 reset functions .................................................................................................................... 49 reset initial conditions ......................................................................................................... 51 input/output ports ......................................................................................... 55 pull-high resistors ................................................................................................................ 55 port a wake-up ..................................................................................................................... 56 i/o port control registers ..................................................................................................... 56 i/o pin structures .................................................................................................................. 58 programming considerations ................................................................................................ 59
rev. 1.10 4 ? a ? ? 0 ? ? 01 ? rev. 1.10 5 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? timer modules C tm ...................................................................................... 60 introduction ........................................................................................................................... 60 t ? operation ........................................................................................................................ 60 t ? clock source ................................................................................................................... 60 t ? interrupts ......................................................................................................................... 60 t ? external pins ................................................................................................................... 61 t ? input/output pin control registers ................................................................................. 61 programming considerations ................................................................................................ 6 ? compact type tm C ctm .............................................................................. 63 compact t ? operation ......................................................................................................... 64 compact t ? pe t ? register description ................................................................................ 64 compact t ? pe t ? operating ? odes .................................................................................... 71 compare ? atch output ? ode ............................................................................................... 71 timer/counter ? ode ............................................................................................................. 74 pw ? output ? ode ................................................................................................................ 74 buzzer control ....................................................................................................................... 76 capture timer module C captm .................................................................. 77 capture timer overview ....................................................................................................... 77 capture timer register description ..................................................................................... 77 capture timer operation ....................................................................................................... 81 infrared receiver ........................................................................................... 82 functional description ........................................................................................................... 8 ? r ? t timing ........................................................................................................................... 8 ? noise filter registers description ......................................................................................... 8 ? remote control timer C r ? t ............................................................................................... 84 r ? t register description ..................................................................................................... 85 analog to digital converter .......................................................................... 86 a/d overview ........................................................................................................................ 86 a/d converter register description ...................................................................................... 87 a/d converter data registers C adrl ? adrh ..................................................................... 87 a/d converter control registers C adcr0 ? adcr1 ? ancsr0 ? ancsr1 ? addl ................. 88 a/d converter boundar ? registers C adlvdl ? adlvdh ? adhvdl ? adhvdh ...................... 91 a/d operation ....................................................................................................................... 9 ? a/d input pins ....................................................................................................................... 9 ? summar ? of a/d conversion steps ....................................................................................... 9 ? programming considerations ................................................................................................ 94 a/d transfer function ........................................................................................................... 94 a/d programming example ................................................................................................... 95 over-current detection .................................................................................. 97 over-current functional description ..................................................................................... 97 over-current register description ......................................................................................... 97
rev. 1.10 4 ?a? ?0? ?01? rev. 1.10 5 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? linear hall sensor detection ........................................................................ 99 hall sensor detection function description .......................................................................... 99 linear hall sensor control register description ................................................................. 100 bldc motor control circuit ........................................................................ 101 functional description ......................................................................................................... 101 pw ? counter control circuit ............................................................................................. 10 ? pw ? register description .................................................................................................. 10 ? ? ask function ..................................................................................................................... 105 register description ............................................................................................................ 108 other functions ................................................................................................................... 109 hall sensor decoder ............................................................................................................ 111 hall sensor decoder register description ........................................................................... 116 ? otor protection function .................................................................................................... 118 ? otor protection function description ................................................................................. 119 ? otor position detection ? ethods ...................................................................................... 1 ?? dc motor control ......................................................................................... 124 ? -pin dc ? otor control ....................................................................................................... 1 ? 4 1-pin dc ? otor control ....................................................................................................... 1 ? 5 register description ............................................................................................................ 1 ? 6 interrupts ...................................................................................................... 127 interrupt registers ............................................................................................................... 1 ? 7 interrupt operation .............................................................................................................. 1 ? 8 external interrupt 0 .............................................................................................................. 140 external interrupt 1 .............................................................................................................. 140 comparator interrupt ........................................................................................................... 140 ? ulti-function interrupt ........................................................................................................ 140 a/d converter interrupt ....................................................................................................... 141 fault interrupt ...................................................................................................................... 141 pause interrupt .................................................................................................................... 141 pw ? ? odule interrupts ...................................................................................................... 141 time base interrupt ............................................................................................................. 14 ? capt ? ? odule interrupt .................................................................................................... 14 ? t ? interrupt ......................................................................................................................... 14 ? r ? t ? odule interrupt ......................................................................................................... 14 ? eepro ? interrupt .............................................................................................................. 14 ? lvd interrupt ....................................................................................................................... 144 interrupt wake-up function ................................................................................................. 144 programming considerations .............................................................................................. 144 low voltage detector C lvd ....................................................................... 145 lvd register ....................................................................................................................... 145 lvd operation ..................................................................................................................... 146
rev. 1.10 6 ? a ? ? 0 ? ? 01 ? rev. 1.10 7 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? application circuits ..................................................................................... 147 hall sensor ? ................................................................................................................... 147 hall sensor 1 ................................................................................................................... 148 non-hall sensor .................................................................................................................. 149 instruction set .............................................................................................. 150 introduction ......................................................................................................................... 150 instruction timing ................................................................................................................ 150 ? oving and transferring data ............................................................................................. 150 arithmetic operations .......................................................................................................... 150 logical and rotate operation ............................................................................................. 151 branches and control transfer ........................................................................................... 151 bit operations ..................................................................................................................... 151 table read operations ....................................................................................................... 151 other operations ................................................................................................................. 151 instruction set summary ............................................................................ 152 table conventions ............................................................................................................... 15 ? instruction defnition ................................................................................... 154 package information ................................................................................... 163 16-pin nsop (150mil) outline dimensions ......................................................................... 16 ? ? 8-pin skdip ( ? 00mil) outline dimensions ........................................................................ 164 ? 8-pin sop ( ? 00mil) outline dimensions ........................................................................... 165 ? 8-pin ssop (150mil) outline dimensions ......................................................................... 166 44-pin qfp (10mm10mm) outline dimensions ................................................................ 167 reel dimensions ................................................................................................................. 168 carrier tape dimensions ..................................................................................................... 169
rev. 1.10 6 ?a? ?0? ?01? rev. 1.10 7 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? features cpu features ? operating voltage: ? f sys =32khz ~ 20mhz: 4.5v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? two oscillators: ? internal 20mhz rc - hirc ? internal 32khz rc - lirc ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 8-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 4k15 ? ram data memory: 2568 ? eeprom memory: 1288 ? watchdog timer function ? up to 28 bidirectional i/o lines ? six pin-shared external interrupts ? support ir cord noise filter function ? four 10-bit ctms for buzzer, rmt, up/down or left/right fan-head ? single 16-bit ctm for bldc sensorless application ? single 16-bit captm for motor protect ? two 8-bit rmts for ir decode ? a pair of 10-bit pwm with comlementary outputs for bldc application ? 9-channel 10-bit resolution a/d converter ? time-base function for generation of fxed time interrupt signal ? single operational amplifer for current detect ? two comparators with interrupt functions ? dual 8-bit d/a converter ? low voltage reset function ? low voltage detect function ? package types: 16-pin nsop, 28-pin sop/ssop/skdip, 44-pin qfp
rev. 1.10 8 ? a ? ? 0 ? ? 01 ? rev. 1.10 9 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? general description this device is flash memory with 8-bit high performance risc architecture microcontroller device which includes a host of fully integrated special features specifcally designed for the brushless dc motor applications. the advantages of low power consumption, i/o fexibility, multiple and extremely fexible timer modules, oscillator op tions, mu lti-channel a/d an d d/a co nverter, pul se wi dth mod ulation function, 16-bit capture timer module function, dual comparator functions, motor protect module, liner hall sensor detection, 8-bit rmt module, time base function, lvd, eeprom, power- down and wake-up functions, although especially designed for brushless dc motor applications, the enhanced versatility of this device also makes it applicable for using in a wide range of a/d application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. block diagram 8-bit risc ?cu core interrupt 10-bit ct?x1 wdt lvr 4kx15 flash ?56x8 ra? ir noise filter vdd vss 1?8x8 eepro? 16-bit capt?x1 bldc ?ctl pb?/rx_in/int1/tp?_0 pa0/an0/int0a pa1/an1/int0b pa?/an?/int0c pa6/an6/fh0_li/tp?_0 pb?/is pc6/fault/tp5_0 pc0/gat pc1/gab pc?/gbt pc?/gbb pc4/gct pc5/gcb pb4/tck? pb0 pb5/tp1_0 pb6/tp0_0 pd1/fh1_sat/tp1_1 pb1/tp?_1 pd0/fh1_sbt/tp0_1 pb7/tck0 pa?/an?/tck5 10-bit ct? & 8-bit r?tx? pc7/pause/tp5_1 pa4/an4/fh0_sat/tck? pa5/an5/fh0_sbt/tp?_1 pa7/an7/fh0_ri/tck1 lvd dac x? & c?p x? opa pd?/fh1_li pd?/fh1_ri 10-bit ct? 10-bit ct? dc ?ctl1 dc ?ctl0 16-bit ct?x1 i/o port 9-ch 10-bit adc x 1
rev. 1.10 8 ?a? ?0? ?01? rev. 1.10 9 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? pin assignment

16-pin nsop pa5/an5/fh0_sbt/tp3_1 pd1/fh1_sbt/tp1_1 ?8 ?7 ?6 ?5 ?4 ?? ?? ?1 ?0 19 18 17 16 15 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 pa3/an3/tck5 pa4/an4/fh0_sat/tck3 pa7/an7/fh0_ri/tck1 pa6/an6/fh0_li/tp3_0 pb3/is vss/avss vdd/avdd pb2/rx_in/int1/tp2_0 pb1/tp2_1 pb0 pc0/gat pc1/gab pc2/gbt pc3/gbb pc4/gct pc5/gcb pd0/fh1_sat/tp0_1 pb7/tck0 pb6/tp0_0 pb5/tp1_0 pb4/tck2 pc6/fault/tp5_0 pc7/pause/tp5_1 pa0/an0/int0a pa1/an1/int0b pa2/an2/int0c 28-pin sop-a/28-pin skdip-a pa5/an5/fh0_sbt/tp3_1 pd1/fh1_sbt/tp1_1 ?8 ?7 ?6 ?5 ?4 ?? ?? ?1 ?0 19 18 17 16 15 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 pa3/an3/tck5 pa4/an4/fh0_sat/tck3 pa7/an7/fh0_ri/tck1 pa6/an6/fh0_li/tp3_0 pb3/is vss/avss vdd/avdd pb2/rx_in/int1/tp2_0 pb1/tp2_1 pb0 pc0/gat pc1/gab pc2/gbt pc3/gbb pc4/gct pc5/gcb pd0/fh1_sat/tp0_1 pb7/tck0 pb6/tp0_0 pb5/tp1_0 pb4/tck2 pc6/fault/tp5_0 pc7/pause/tp5_1 pa0/an0/int0a pa1/an1/int0b pa2/an2/int0c 28-pin ssop-a
rev. 1.10 10 ? a ? ? 0 ? ? 01 ? rev. 1.10 11 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? nc pb3/is avss vss avdd vdd pb2/rx_in/int1/tp2_0 pb1/tp2_1 nc nc nc pb0 pc0/gat pc1/gab pc2/gbt pc3/gbb pc4/gct pc5/gcb pd0/fh1_sat/tp0_1 pd1/fh1_sbt/tp1_1 pd2/fh1_li pd3/fh1_ri nc nc nc pb7/tck0 pb6/tp0_0 pb5/tp1_0 pb4/tck2 nc nc nc nc pa0/an0/int0a pa1/an1/int0b pa2/an2/int0c pa5/an5/fh0_sbt/tp3_1 pa3/an3/tck5 pa4/an4/fh0_sat/tck3 nc 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 15 16 17 18 19 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ? 940414? 4? 44 pa7/an7/fh0_ri/tck1 pc6/fault/tp5_0 pc7/pause/tp5_1 pa6/an6/fh0_li/tp3_0 44-pin qfp-a note: 1. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority 2. vdd&avdd means the vdd and avdd are the double bonding. 3. vss&avss means the vss and avss are the double bonding.
rev. 1.10 10 ?a? ?0? ?01? rev. 1.10 11 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? pin description pin name function op i/t o/t description pa0/an 0/ int0a pa0 pawu papu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. an0 ancsr0 an a/d channel 0 int0a intc0 st external interrupt input pa1/an1/ int0b pa1 papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. an1 ancsr0 an a/d channel 1 int0b intc0 st external interrupt input pa ? /an ? / int0c pa ? papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. an ? ancsr0 an a/d channel ? int0c intc0 st external interrupt input pa ? /an ? / tck5 pa ? papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. an ? ancsr0 an a/d channel ? tck5 st t ? 5 input pa4/an4/ fh0_sat /tck ? pa4 papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. an4 ancsr0 an a/d channel 4 fh0_sat dc ? cr1 dc fan head port output tck ? st t ?? input pa5/an5/ fh0_sbt/ tp ? _1 pa5 papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. an5 ancsr0 an a/d channel 5 fh0_sbt dc ? cr1 dc fan head port output tp ? _1 t ? pc0 st c ? os t ?? i/o pa6/an6/ fh0_li/ tp ? _0 pa6 papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. an6 ancsr0 an a/d channel 6 fh0_li dc ? cr1 dc fan head port output tp ? _0 t ? pc0 st c ? os t ?? i/o pa7/an7/ fh0_ri /tck1 pa7 papu pawu st c ? os bidirectional 8-bit i/o port. register enabled pull-up and wake-up. an7 ancsr0 an a/d channel 7 fh0_ri dc ? cr1 dc fan head port output tck1 st c ? os t ? 1 input pb0 pb0 pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. pb1/tp ? _1 pb1 pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tp ? _1 t ? pc0 c ? os t ?? i/o
rev. 1.10 1 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 1? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? pin name function op i/t o/t description pb ? /rx_in/ int1/tp ? _0 pb ? pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. rx_in intc0 st ir receive input pin int1 intc0 st external interrupt input tp ? _0 t ? pc0 st c ? os t ?? i/o pb ? /is pb ? pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. is opo ? s st operational amplifer input pin pb4/tck ? pb4 pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tck ? st t ?? input pb5/tp1_0 pb5 pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tp1_0 t ? pc0 st c ? os t ? 1 i/o pb6/tp0_0 pb6 pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tp0_0 t ? pc0 st c ? os t ? 0 i/o pb7/tck0 pb7 pbpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. tck0 st t ? 0 input pc0/gat pc0 pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. gat pw ? c c ? os pulse width ? odulation complimentar ? output pc1/gab pc1 pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. gab pw ? c c ? os pulse width ? odulation complimentar ? output pc ? /gbt pc ? pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. gbt pw ? c c ? os pulse width ? odulation complimentar ? output pc ? /gbb pc ? pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. gbb pw ? c c ? os pulse width ? odulation complimentar ? output pc4/gct pc4 pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. gct pw ? c c ? os pulse width ? odulation complimentar ? output pc5/gcb pc5 pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. gcb pw ? c c ? os pulse width ? odulation complimentar ? output pc6/fault/ tp5_0 pc6 pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. fault ? ptc1 st pw ? disable input pin. active low tp5_0 t ? pc1 st c ? os capt ? i/o
rev. 1.10 1? ?a? ?0? ?01? rev. 1.10 1 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? pin name function op i/t o/t description pc7/pause/ tp5_1 pc7 pcpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. pause ? ptc1 st pw ? pause input pin tp5_1 t ? pc1 st c ? os capt ? i/o pd0/ fh1_sat/ tp0_1 pd0 pdpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. fh1_sat dc ? cr1 dc fan head port output tp0_1 t ? pc0 st c ? os t ? 0 i/o pd1/ fh1_sbt/ tp1_1 pd1 pdpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. fh1_sbt dc ? cr1 dc fan head port output tp1_1 t ? pc0 st c ? os t ? 1 i/o pd ? /fh1_li pd ? pdpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. fh1_li dc ? cr1 dc fan head port output pd ? /fh1_ri pd ? pdpu st c ? os bidirectional 8-bit i/o port. register enabled pull-up. fh1_ri dc ? cr1 dc fan head port output vss vss pwr negative power suppl ?? ground avss avss pwr ground connection for a/d converter. the vss and avss are the same pin at ? 8 pin package vdd vdd pwr positive power suppl ? avdd avdd pwr power suppl ? connection for a/d converter. the vdd and avdd are the same pin at ? 8 pin package note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger in put cmos: cmos output; nmos: nmos output an: analog input pin vdd is the device power supply while avdd is the adc power supply . vss is the device ground pin while avss is the adc ground pin. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins.
rev. 1.10 14 ? a ? ? 0 ? ? 01 ? rev. 1.10 15 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? absolute maximum ratings supply voltage ................................................................................................ v ss ?0.3v to v ss +6.0v input voltage .................................................................................................. v ss ? 0.3v to v dd +0.3v storage temperature .................................................................................................... -50? c to 125?c operating temperature .................................................................................................. -40?c to 85?c i oh total .................................................................................................................................... -80ma i ol total ..................................................................................................................................... 80ma total power dissipation ........................................................................................................ 500mw note: these are str ess rat ings only . str esses exc eeding the range spec ified unde r "absolu te max imum ratings" may cause substantial damage to this device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect devices reliability. d.c. characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys = ?? ~ ? 0000khz 4.5 5.5 v i dd operating current (hirc osc) 5v no load ? f h = ? 0 ? hz ? adc off ? wdt enable ? ? otor_ctl off ? ir_rx off 8 10 ma i stb standb ? current lirc and lvr on ? lvd off ? wdt enable 60 100 v il input low voltage for i/o ports ? tckn ? int0a ? int0b ? int0c ? int1 0 0. ? v dd v v ih input high voltage for i/o ports ? tckn ? int0a ? int0b ? int0c ? int1 0.7v dd v dd v v lvr lvr voltage level lvr enable ? ? .15v option -5% ? .15 +5% v v lvd lvd voltage level lvden=1 ? v lvd = ? .6v -5% ? .6 +5% v v ol output low voltage for i/o ports 5v i ol = ? 0ma 0.5 v v oh output high voltage for i/o ports 5v i oh =-7.4ma 4.5 v r ph pull-high resistance for i/o ports 5v 10 ? 0 50 n
rev. 1.10 14 ?a? ?0? ?01? rev. 1.10 15 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? a.c. characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions f sys s ? stem clock 4.5v~5.5v ?? ? 0000 khz f hirc s ? stem clock (hirc) 4.5v~5.5v ta=-40?c~85?c -1 ? % ? 0 +4% ? hz ta=-20?c~85?c -9% ? 0 +4% ? hz ta=25?c - ? % ? 0 + ? % ? hz f ti ? er timer input pin frequenc ? 1 f sys t int interrupt pulse width 1 t sys t lvr low voltage width to reset 1 ? 0 ? 40 480 s t lvd low voltage width to interrupt ? 0 45 90 s t lvds lvdo stable time 15 s t eerd eepro ? read time 45 90 s t eewr eepro ? write time ? 4 ms t sst s ? stem start-up timer period (wake-up from halt) f sys =hirc 15~16 t sys t rstd s ? stem reset dela ? time (power on reset) ? 5 50 100 ms s ? stem reset dela ? time (an ? reset except power on reset) 8. ? 16.7 ?? . ? ms 1rwh w 66 i 66 7r pdlqwdlq wkh dffxudf ri wkh lqwhuqdo +?5& rvfloodwru iuhtxhqf d ) ghfrxsolqj fdsdflwru vkrxog eh frqqhfwhg ehwzhhq 9'' dqg 966 dqg orfdwhg dv forvh wr wkh ghylfh dv srvvleoh
rev. 1.10 16 ? a ? ? 0 ? ? 01 ? rev. 1.10 17 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? a/d converter characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd condition av dd a/d converter operating voltage v lvr 5.0 5.5 v i op a/d converter operating current ? v 0.8 ma 5v 1 ma i stby adc standb ? current digital input no change 1 a v ref a/d converter reference voltage ? av dd av dd +0.1 v t conv a/d conversion time 14 t adck dnl a/d differential non-linearit ? ? lsb inl a/d integral non-linearit ? ? lsb g err gain error ? lsb t adck adclk period 0.166 s t ckh adclk high width 8 ? ns t ckl adclk low width 8 ? ns t st1 setup time for adon ? ns t st ? setup time for start latch ? ns t sth start high width ? 5 ns t deoc eocb output dela ? av dd =5v ? ns t dout output dela ? av dd =5v ? ns t on adc wake up time ? s t off adc sleep time 5 ns d/a converter characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions v dd d/a operating current v lvr 5.5 v v da d/a output voltage 00h ~ ffh ? no load 0.01 0.99 v dd t dac d/a conversion time v dd =5v ? c l =10p ? s r o d/a output resistance 10 k 8-bit r- ? r d/a converter(analog conditon v dd =5v ? c l =10p) model corner tt sf fs ss ff temperature ? 5 ? 5 ? 5 90 -40 operating average current (v dd =5v ? c l =10p) 352a 330a 374a 297a 413a analog output 00000000 (b) ~11111111 (b) 0~4.98v 0~4.981v 0~4.98v 0~4.98v 0~4.981v conversion time 2s 2s 2s 2s 2s
rev. 1.10 16 ?a? ?0? ?01? rev. 1.10 17 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? operational amplifer characteristics tac symbol parameter test conditions min. typ. max. unit v dd conditions i opr1 operating current 5v ? 50 i off1 power down current 5v 0.1 v opos1 input offset voltage 5v without calibration ? opof[ ? :0]=1000b -15 +15 mv v opos ? input offset voltage 5v b ? calibration -4 +4 mv v c ? common ? ode voltage range v ss v dd -1.4v v psrr power suppl ? rejection ratio 5v 60 80 db c ? rr common ? ode rejuction ratio 5v v c ? =0 ~ v dd -1.4v 60 80 db sr slew rate+ ? slew rate- 5v no load 1.8 ? .5 9v gbw gain band width 5v r l 0& l =100pf ? .5 ? hz comparator electrical characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd condition i opr0 comparator operating voltage 5v ? 00 ? 00 i off0 comparator power down current 5v 0.1 v os comparator input offset voltage -10 +10 mv v c ? comparator common mode input voltage range v ss v dd -1.4v v t pd comparator response time (100mv overdrive) 4 8 v power on reset electrical characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd condition v por v dd start voltage to ensure power-on reset 100 mv rr vdd v dd rise rate to ensure power-on reset 0.0 ? 5 v/ms t por ? inimum time for v dd to remain at v por to ensure power-on reset 1 ms
rev. 1.10 18 ? a ? ? 0 ? ? 01 ? rev. 1.10 19 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining sche me is im plemented in such a way tha t inst ruction fet ching and inst ruction execution are overla pped, hence inst ructions are ef fectively exec uted in one cycl e, wit h the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o an d a/d co ntrol syst em wit h ma ximum re liability an d fl exibility. th is ma kes th is device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main syst em cl ock, de rived fr om ei ther a hir c or li rc osc illator is sub divided in to fo ur internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cyc les, th e pipe lining stru cture of th e mi crocontroller ensu res th at in structions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obta in the ac tual jum p or ca ll addre ss and the n anot her cyc le to ac tually exe cute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? system clocking and pipelining
rev. 1.10 18 ?a? ?0? ?01? rev. 1.10 19 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ?
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program exe cution, the progra m count er is used to kee p tra ck of the addre ss of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed ex cept for in structions, suc h as jmp or c all th at de mand a ju mp to a non-consecutive pro gram mem ory ad dress. onl y th e lo wer 8 bi ts, kn own as th e pro gram co unter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine ca ll, int errupt or reset , et c., the mi crocontroller ma nages program cont rol by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc11~pc8 pcl7~pcl0 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a sho rt pr ogram ju mp ca n be ex ecuted di rectly; ho wever, as on ly th is lo w by te is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.10 ? 0 ? a ? ? 0 ? ? 01 ? rev. 1.10 ?1 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has eight levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or ret i, the program counte r is rest ored to it s previ ous val ue from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly upgrated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.10 ?0 ?a? ?0? ?01? rev. 1.10 ? 1 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? flash program memory the program memory is the location where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, this flash device offer users the fexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. structure the program mem ory has a ca pacity of 4k15 bit s. the program mem ory is addre ssed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by th is de vice rese t for prog ram in itialisation. afte r a dev ice rese t is initiated, the program will jump to this location and begin execution.
program memory structure look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the "tabrdc [m]" or "tabrdl [m]" instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.

rev. 1.10 ?? ? a ? ? 0 ? ? 01 ? rev. 1.10 ?? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "f00h" which refers to the start address of the last page within the 4k program memory of the device. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "f06h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "tabrdc [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "t abrdc [m]" instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; i nitialise low table pointer - note that this address ; is referenced mov tblp, a ; t o the last page or present page mov a, 07h ; initialise high table pointer mov tbhp, a : : tabrdl tempreg1 ; t ransfers value in table referenced by table pointer ; data at program memory address f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; t ransfers value in table referenced by table pointer ; data at program memory address f05h transferred to ; tempreg2 and tblh in this example the data 1ah is ; t ransferred to tempreg1 and data 0fh to register tempreg2 : : org f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.10 ?? ?a? ?0? ?01? rev. 1.10 ?? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? in circuit programming the provision of fla sh ty pe pro gram mem ory pr ovides th e use r wit h a me ans of co nvenient an d easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upg rading th e pro gram at a la ter sta ge. th is e nables p roduct ma nufacturers t o ea sily keep their manufactured products sup plied with the latest program releases without removal and re-insertion of the device. mcu programming pins function pa0 serial data input/output pa ? serial clock pb0 in circuit programming ? ode set vdd power suppl ? vss ground the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and in circuit programming mode set. the technical details regarding the incircuit programming of the device is beyond the scope of this document and will be supplied in supple mentary literature. during the programming process the pb0 pin will be used to set the in circuit programing mode and taking control of the pa0 and pa2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. programmer pin mcu pins icp ? s pb0 icpda pa0 icpck pa ? programmer and mcu pins
rev. 1.10 ? 4 ? a ? ? 0 ? ? 01 ? rev. 1.10 ?5 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. the capacity of this device is 2568. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. her e ar e lo cated re gisters whi ch ar e ne cessary fo r co rrect op eration of th e de vice. man y of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory, which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. 00h 7fh 80h ffh data memory structure
rev. 1.10 ?4 ?a? ?0? ?01? rev. 1.10 ? 5 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ?

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rev. 1.10 ? 6 ? a ? ? 0 ? ? 01 ? rev. 1.10 ?7 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal regist ers. the me thod of i ndirect addre ssing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from ba nk 0 whi le t he iar1 and mp1 regist er pa ir c an access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory poi nters, kn own as mp0 an d mp1 ar e pr ovided. th ese mem ory poi nters ar e physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data fro m a ll ba nks a ccording to b p re gister. di rect addre ssing ca n onl y b e use d wi th ba nk 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 0 0h start: mov a,04h ; setup size of block mov block,a mov a, offset adre s1 ; ac cumulator lo aded wi th fr st ra m add ress mov mp 0,a ; se tup me mory poi nter wit h fr st ra m ad dress loop: clr ia r0 ; cl ear th e da ta at add ress de fned by mp 0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc ram addresses.
rev. 1.10 ?6 ?a? ?0? ?01? rev. 1.10 ? 7 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? bank pointer C bp the data memory is divided into two banks. selecting the data memory area is achieved using the bank pointer. bit 0 of the bank pointer is used to select data memory banks 0 or 1. the data mem ory is ini tialised to bank 0 aft er a rese t, exc ept for a wdt ti me-out rese t in the power down mode, in which case, the data memory bank remains unaffected. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing. bp register bit 7 6 5 4 3 2 1 0 name d ? bp0 r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 dmbp0: select data memory banks 0: bank 0 1: bank 1 accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logic al opera tion such as addit ion, subtrac tion, shift , etc ., to the data mem ory resulting in higher programm ing and tim ing overheads. data tra nsfer operations usually invol ve the temporary stora ge funct ion of the acc umulator; for ex ample, whe n tra nsferring dat a bet ween one user defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted.
rev. 1.10 ? 8 ? a ? ? 0 ? ? 01 ? rev. 1.10 ?9 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program mem ory. tbl p and tbhp are the ta ble point er and indi cates the loc ation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the "clr wdt" or "halt" instruction. the pdf fag is affected only by executing the "halt" or "clr wdt" instruction or during a system power -up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or hal t instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.10 ?8 ?a? ?0? ?01? rev. 1.10 ? 9 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x" unknown bit 7, 6 unimplemented, read as 0 bit 5 to: watchdog time-out fag 0: after power up or executing the clr wdt or hal t instruction 1: a watchdog time-out occurred. bit 4 pdf: power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.10 ? 0 ? a ? ? 0 ? ? 01 ? rev. 1.10 ?1 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? system control register C ctrl bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 " x" unknown bit 7 fsyson: f sys control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag 0: not occurred 1: occurred this bit can be cleared to 0, but can not be set to 1. bit 1 lrf: lvr control register software reset fag 0: not occurred 1: occurred this bit can be cleared to 0, but can not be set to 1. bit 0 wrf: wdt control register software reset fag 0: not occurred 1: occurred this bit can be cleared to 0, but can not be set to 1.
rev. 1.10 ?0 ?a? ?0? ?01? rev. 1.10 ? 1 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? eeprom data memory the device contains an area of internal eeprom data memory. eeprom, which stands for electrically era sable program mable rea d only mem ory, is by it s nat ure a non-vola tile form of re-programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application poss ibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 1288 bits. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register. the eec register however, being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are executed. eeprom register list name bit 7 6 5 4 3 2 1 0 eea d6 d5 d4 d ? d ? d1 d0 eed d7 d6 d5 d4 d ? d ? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x unknown bit 7 unimplemented, read as 0 bit 6~0 data eeprom address data eeprom address bit 6~bit 0
rev. 1.10 ?? ? a ? ? 0 ? ? 01 ? rev. 1.10 ?? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 undefned, read as 0 bit 3 wren: data eeprom write enable 0: disable 1: enable this is the data eepro m write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr: eeprom write control 0: write cycle has fnished 1: activate a write cycle this is the dat a ee prom wr ite co ntrol bi t an d whe n set hi gh by th e ap plication program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no effect if the wren has not frst been set high. bit 1 rden: data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. reading data from the eeprom to read data from the eepro m, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is exe cuted. the app lication progr am ca n pol l th e rd bit to det ermine when th e dat a is valid for reading.
rev. 1.10 ?? ?a? ?0? ?01? rev. 1.10 ?? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? writing data to the eeprom to write data to the ee prom, the wri te ena ble bit , wre n, in the ee c regi ster must frst be set high to enable the write function. the eepro m address of the data to be written must then be placed in the eea register and the data placed in the eed register. if the wr bit in the eec register is now set high, an internal write cycle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be im plemented ei ther by poll ing the wr bit in the ee c regi ster or by using the eeprom interrupt. wh en th e wri te cy cle te rminates, th e wr bi t wil l be au tomatically cl eared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on th e wr ite en able bi t in th e co ntrol re gister wil l be cl eared pr eventing an y wri te operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write or read interrupt is generated when an eeprom write or read cycle has ended. the eeprom interrupt must first be enabled by setting the epwe bit in the relevant interrupt register. howeve r as the ee prom is cont ained wit hin a mult i-function inte rrupt, the assoc iated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the epwf request fag and its associated multi-function interrupt request fag will both be set. if the global, eepro m and multi-function interrupts are enabled and the stack is not full, a jump to the associated mult i-function inte rrupt vec tor wil l ta ke pla ce. whe n the int errupt is servi ced only the multi-function interrupt fag will be automatic ally reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section. programming consideration care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process.
rev. 1.10 ? 4 ? a ? ? 0 ? ? 01 ? rev. 1.10 ?5 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? programming examples reading data from the eeprom C polling method mov a, eep rom_adres ; us er de fned add ress mov eea, a mov a, 040h ; se tup me mory po inter mp 1 mov mp1, a ; m p1 po ints to ee c re gister mov a, 01h ; se tup ba nk po inter mov bp, a set iar1.1 ; se t rd en bi t, en able re ad op erations set iar1.0 ; st art re ad cy cle - se t rd bi t back: sz iar1.0 ; ch eck fo r re ad cy cle en d jmp back clr iar1 ; di sable ee prom re ad/write clr bp mov a, eedata ; mo ve r ead dat a to r egister mov read_data, a writing data from the eeprom C polling method mov a, eep rom_adres ; us er de fned add ress mov eea, a mov a, eeprom_data ; us er def ned dat a mov eed, a mov a, 040h ; se tup me mory po inter mp 1 mov mp1, a ; mp 1 po ints to ee c re gister mov a, 01h ; se tup ba nk po inter mov bp, a set iar1.3 ; se t wr en bit , en able wr ite op erations set iar1.2 ; st art wr ite cy cle - se t wr bi t back: sz iar1.2 ; ch eck fo r wr ite cy cle en d jmp back clr iar1 ; di sable ee prom re ad/write clr bp
rev. 1.10 ?4 ?a? ?0? ?01? rev. 1.10 ? 5 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupt. fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the higher fr equency osc illator pr ovides hi gher pe rformance bu t ca rry wit h it th e di sadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, this device have the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. internal high speed rc hirc ? 0 ? hz internal low speed rc lirc ?? khz oscillator types system clock confgurations there are two methods of generating the system clock, a high speed oscill ator and a low speed oscillator. the high speed oscillator is the internal 20mhz rc oscillator . the low speed oscillator is the internal 32khz rc oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. hirc li rc hi gh sp ee d o sci ll at io n lo w sp ee d o sci ll at io n f h f h /6 4 f h /3 2 f h /1 6 f h /8 f h /4 f h /2 6- st age pr es ca le r f l f sub f sys hlcl k, ck s2 ~c ks 0 bi ts system clock confgurations
rev. 1.10 ? 6 ? a ? ? 0 ? ? 01 ? rev. 1.10 ?7 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? internal 20mhz rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequencies of 20mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 20mhz will have a tolerance within 2%. internal 32khz oscillator C lirc the internal 32khz system oscillator is a low frequency oscillator choice. it is a fully integrated rc oscillator wit h a typi cal freque ncy of 32khz at 5v, requi ring no ext ernal com ponents for it s implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. supplementary clocks the low speed oscillator, in addition to providing a system clock source are also used to provide a clock source to other device functions. these are the watchdog timer and the time base interrupt.
rev. 1.10 ?6 ?a? ?0? ?01? rev. 1.10 ? 7 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? operating modes and system clocks present day applicati ons require that their microcontrol lers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powere d port able appl ications. the fast cl ocks requi red for high perform ance wil l by their nature inc rease curr ent consu mption and of cour se vic e versa , lowe r spee d cl ocks redu ce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed sys tem clock can be sourced from hirc oscillator. the low speed system clock source can be sourced from internal clock f l . if f l is selected then it can be sourced by the lirc oscillator. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the time base clock, f tbc . each of these internal clocks is sourced by the lirc oscillator. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times.
rev. 1.10 ? 8 ? a ? ? 0 ? ? 01 ? rev. 1.10 ?9 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. the f s is used as the clock source for the w atchdog timer. t ogether with f sys /4, the f tbc clock is also used as a source for the time base interrupt function and for the tms.
rev. 1.10 ?8 ?a? ?0? ?01? rev. 1.10 ? 9 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? system operation modes there are five di fferent mo des of ope ration for th e mi crocontroller, ea ch one wit h it s own special characteristics and which can be chosen according to the specific performance and power requirements of the applicat ion. there are two modes allowi ng normal operation of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f sub f s f tbc nor ? al ? ode on f h ~f h /64 on on on slow ? ode on f l on on on idle0 ? ode off off on on on idle1 ? ode off on on on on sleep ? ode off off on on on ? normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. this mode operates allowing the microcontroller to operate normally with a clock source will come from hirc oscillator. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. ? slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from the low speed oscillator, lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. ? sleep mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep mode the cpu will be stopped. ? idle0 mode the idle0 mode is ent ered when a halt inst ruction is exe cuted and when the idle n bit in the smod register is high and the fsyson bit in the ctrl register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer and tms. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the watchdog timer clock, f s , will be always on. ? idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watchdog timer and tms. in the idle1 mod e, th e syst em osc illator wil l co ntinue to ru n, an d th is syst em osc illator ma y be high speed or low speed system oscillator. in the idle1 mode the watchdog timer clock, f s , will be on.
rev. 1.10 40 ? a ? ? 0 ? ? 01 ? rev. 1.10 41 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? control register a single register , smod, is used for overall control of the internal clocks within this device. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 cks2~cks0: the system clock selection when hlclk is 0 000: f l (f lirc ) 001: f l (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be the lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten: fast wake-up control 0: disable 1: enable this is the fast wa ke-up co ntrol bi t whi ch de termines if the f sub clock source is initially used after this device wake up. when the bit is high, the f sub clock source can be used as a temporary system clock to provide a faster wake up time as the f sub clock is available. bit 3 lto: low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will change to a high level after 1~2 clock cycles if the lirc oscillator is used. bit 2 hto: high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when this device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 15~16 clock cycles if the hirc oscillator is used. bit 1 idlen: idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed this device will en ter th e idl e mod e. in th e idl e1 mod e th e cpu wil l stop run ning but the system cl ock wil l cont inue to kee p the peri pheral func tions ope rational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low this device will enter the sleep mode when a hal t instruction is executed.
rev. 1.10 40 ?a? ?0? ?01? rev. 1.10 41 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? bit 0 hlclk: system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. fast wake-up to minimise power consumption this device can enter the sleep or idle0 mode, where the system clock source to this device will be stopped. however when this device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. to ensure the devi ce is up and running as fast as possibl e a fast wa ke-up funct ion is provided, which allows f sub , namely the lirc oscillator, to act as a temporary clock to f rst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep and idle0 modes. the fast wake-up enable/disable function is controlled using the fsten bit in the smod register . if the hirc oscillator or lirc oscillator is used as the system oscillator then it will take 15~16 clock cycles of the hirc or 1~2 cyc les of the lirc to wake up the syste m from the sle ep or idle0 mode. the fast wake-up bit, fsten will have no ef fect in these cases. system oscillator fsten bit wake-up time (sleep mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hirc x 15~16 hirc c ? cles 1~ ? hirc c ? cles lirc x 1~ ? lirc c ? cles 1~ ? lirc c ? cles wake-up times
rev. 1.10 4 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 4? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ?

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rev. 1.10 4? ?a? ?0? ?01? rev. 1.10 4 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? operating mode switching and wake-up this device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is exe cuted, whet her thi s devi ce ent er the idle mode or the sle ep mode is determined by the condition of the idlen bit in the smod register and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h, to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms. the accompanying fowchart shows what happens when this device move between the various operating modes. normal mode to slow mode switching when running in th e normal mod e, whi ch use s th e hi gh spe ed syst em osc illator, an d th erefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the l to bit in the smod register . slow mode to normal mode switching in slow mode the system uses the lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 011, 100, 101, 110 or 11 1. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
rev. 1.10 44 ? a ? ? 0 ? ? 01 ? rev. 1.10 45 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ?
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rev. 1.10 44 ?a? ?0? ?01? rev. 1.10 45 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? entering the sleep mode there is only one way for this device to enter the sleep mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle0 mode there is only one way for this device to enter the idle0 mode and that is to execute the halt instruction in th e ap plication pr ogram wit h th e idl en bi t in smod re gister eq ual to 1 an d th e fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the time base clock and f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle1 mode there is only one way for this device to enter the idle1 mode and that is to execute the halt instruction in th e ap plication pr ogram wit h th e idl en bi t in smod re gister eq ual to 1 an d th e fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock and f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared.
rev. 1.10 46 ? a ? ? 0 ? ? 01 ? rev. 1.10 47 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of this device to as low a val ue as possible , perha ps only in the order of seve ral mi cro-amps exc ept in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consum ption is to be mi nimised. spec ial at tention must be ma de to the i/o pins on this device. all high-impedance input pins must be connected to either a fxed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonded pins. these must eithe r be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, this device will experience a full system reset, however, if this device are woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pa wu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execut ion at the instruction fol lowing th e hal t in struction. if th e syst em is woke n up by an in terrupt, th en two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up this device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before ente ring the sleep or idle mode, the wake -up functi on of the rela ted interrupt will be disabled.
rev. 1.10 46 ?a? ?0? ?01? rev. 1.10 47 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock, f s , which can be sourced from the lirc oscillator. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. watchdog timer control register a single register, wdtc, controls the overall operation of the watchdog timer . any reset of this device, the initial value of the wdtc is always 01010011, and it will not be changed in power down mode. wdtc register bit 7 6 5 4 ? ? 1 0 name we4 we ? we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4~we0 : wdt operation 10101 or 01010: enable other values: mcu reset (reset will be active after 1~2 lirc clock for debounce time.) if the mcu rese t ca used by the we [4:0] in wdtc softwa re rese t, the wrf fag of ctrl register will be set) bit 2~0 ws2~ws0 : wdt time-out period selection 000: 2 8 /f s 001: 2 10 /f s 010: 2 12 /f s 011: 2 14 /f s 100: 2 15 /f s 101: 2 16 /f s 110: 2 17 /f s 111: 2 18 /f s these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period.
rev. 1.10 48 ? a ? ? 0 ? ? 01 ? rev. 1.10 49 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? watchdog timer operation note that the watchdog timer function is always enabled. the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instruction. if the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. there are fve bits, we4~we0, in the wdtc register to offer a control of the watchdog timer . if we4~we0 bits are set to a specifc value of "10101" or "01010", the wdt is alway enable. any other values for these bits will keep the mcu reset. under normal program opera tion, a wa tchdog ti mer ti me-out wil l ini tialise a devi ce rese t and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer . the frst is an external hardware reset, the second is using the watchdog timer software clear instruction and the third is via a halt instruction. to clear the watchdog timer is to use the single clr wdt instruction. a simple execution of "clr wdt" will clear the wdt.
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rev. 1.10 48 ?a? ?0? ?01? rev. 1.10 49 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller , after a short delay, will be in a well defined state and ready to execute the frst pr ogram in struction. aft er th is po wer-on re set, ce rtain im portant in ternal re gisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, l vr, where the power supply voltage falls below a certain threshold. reset functions there are four ways in which a microcontroller reset can occur, through events occurring both internally and externally: ? power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. vdd power-on reset sst time-out t rstd note: t rstd is power-on delay, typical time=50ms power-on reset timing chart ? low voltage reset C l vr this microcontroller co ntains a lo w vo ltage re set ci rcuit in or der to mo nitor th e sup ply vo ltage of this device, whic h is cont rolled by lvrc regi ster. if the supply volt age of the devi ce drops to within a ra nge of 0. 9v~v lvr such as might oc cur whe n ch anging th e ba ttery, th e lvr wil l automatically reset the device internally and set the lvrf in the ctrl register to high .the lvr includes the following specifcations: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not exceed t lvr , the lvr will ignore it and will not perform a reset function. note: t rstd is power-on delay, typical time=16.7ms low voltage reset timing chart
rev. 1.10 50 ? a ? ? 0 ? ? 01 ? rev. 1.10 51 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? lvrc register bit 7 6 5 4 ? ? 1 0 name lvs7 lvs6 lvs5 lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~3 lvs7~lvs0 : lvr voltage select 01010101: 3.15v 00110011: 3.15v 10011001: 3.15v 10101010: 3.15v other values: mcu reset (reset will be active after 2~3 lirc clock for debounce time.) if the mcu reset caused by the lvrc software reset, the lrf fag of ctrl register will be set. ? watchdog time-out reset during normal operation the watchdog time-out fag to will be set to 1. note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart ? watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by hirc. the t sst is 1~2 clock for lirc. wdt time-out reset during sleep or idle timing chart
rev. 1.10 50 ?a? ?0? ?01? rev. 1.10 51 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer . the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset u u lvr reset during nor ? al or slow ? ode operation 1 u wdt time-out reset during nor ? al or slow ? ode operation 1 1 wdt time-out reset during idle or sleep ? ode operation u stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset ? wdt begins counting timer/event counter t ? modules will be turned off input/output ports i/o ports will be setup as inputs ? and an0~an7 is as a/d input pin. stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what co ndition th e mi crocontroller is in af ter a pa rticular re set oc curs. th e fo llowing ta ble describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (idle) ? p0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ? p1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu tblh -xxx xxxx -uuu uuuu -xxx xxxx -uuu uuuu tbhp ---- xxxx ---- uuuu ---- xxxx ---- uuuu status --00 xxxx --1u uuuu --uu xxxx --11 uuuu s ? od 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc --00 -000 --00 -000 --00 -000 --uu Cuuu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu intc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu ? fi0 -000 -000 -000 -000 -000 -000 -uuu -uuu
rev. 1.10 5 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 5? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (idle) ? fi1 --00 --00 --00 --00 --00 --00 --uu C-uu ? fi ? --00 --00 --00 --00 --00 --00 --uu --uu ? fi ? --00 --00 --00 --00 --00 --00 --uu --uu ? fi4 0000 0000 0000 0000 0000 0000 uuuu uuuu ? fi5 0000 0000 0000 0000 0000 0000 uuuu uuuu ? fi6 -000 -000 -000 -000 -000 -000 -uuu -uuu ? fi7 --00 --00 --00 --00 --00 --00 --uu --uu ? fi8 --00 --00 --00 --00 --00 --00 --uu --uu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pdpu ---- 0000 ---- 0000 ---- 0000 ---- uuuu pd ---- 1111 ---- 1111 ---- 1111 ---- uuuu pdc ---- 1111 ---- 1111 ---- 1111 ---- uuuu nf_vih 0--11001 0--11001 0--11001 u--u uuuu nf_vil ---0 1010 ---0 1010 ---0 1010 ---u uuuu r ? tc 0000 0000 0000 0000 0000 0000 uuuu uuuu r ? t0 0000 0000 0000 0000 0000 0000 uuuu uuuu r ? t1 0000 0000 0000 0000 0000 0000 uuuu uuuu hchk_nu ? ---0 0000 ---0 0000 ---0 0000 ---u uuuu hnf_ ? sel ---- 0000 ---- 0000 ---- 0000 ---- uuuu captc0 0000 0000 0000 0000 0000 0000 uuuu uuuu captc1 0000 0000 0000 0000 0000 0000 uuuu uuuu capt ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu capt ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu capt ? al 0000 0000 0000 0000 0000 0000 uuuu uuuu capt ? ah 0000 0000 0000 0000 0000 0000 uuuu uuuu capt ? cl xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu capt ? ch xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu opo ? s 00-- -010 00-- -010 00-- -010 uu-- -uuu opc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu lh ? c --00 --00 --00 --00 --00 --00 --uu --uu hac ? 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? pc0 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? pc1 ---- --00 ---- --00 ---- --00 ---- --uu ctrl 0--- -x00 0--- -x00 0--- -x00 u--- -uuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu eea -xxx xxxx -xxx xxxx -xxx xxxx -uuu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrl xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
rev. 1.10 5? ?a? ?0? ?01? rev. 1.10 5 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (idle) adrh ---- --xx ---- --xx ---- --xx ---- --uu adcr0 011- 0000 011- 0000 011- 0000 uuu- uuuu adcr1 0000 0000 0000 0000 0000 0000 uuuu uuuu ancsr0 1111 1111 1111 1111 1111 1111 uuuu uuuu ancsr1 ---- ---1 ---- ---1 ---- ---1 ---- ---u addl 0000 0000 0000 0000 0000 0000 uuuu uuuu adlvdl 0000 0000 0000 0000 0000 0000 uuuu uuuu adlvdh xxxx xx00 xxxx xx00 xxxx xx00 uuuu uuuu adhvdl 0000 0000 0000 0000 0000 0000 uuuu uuuu adhvdh ---- --00 ---- --00 ---- --00 ---- --uu pw ? c --00 0--0 --00 0--0 --00 0--0 --uu u--u dutrl 0000 0000 0000 0000 0000 0000 uuuu uuuu dutrh ---- --00 ---- --00 ---- --00 ---- --uu prdrl 0000 0000 0000 0000 0000 0000 uuuu uuuu prdrh 0000 0000 0000 0000 0000 0000 uuuu uuuu pw ? rl 0000 0000 0000 0000 0000 0000 uuuu uuuu pw ? rh ---- --00 ---- --00 ---- --00 ---- --uu ? cf ---- 0100 ---- 0100 ---- 0100 ---- uuuu ? cd --00 0000 --00 0000 --00 0000 --uu uuuu dts 0000 0000 0000 0000 0000 0000 uuuu uuuu plc --00 0000 --00 0000 --00 0000 --uu uuuu hdcr 0001 0000 0001 0000 0001 0000 uuuu uuuu hdcd ---- -000 ---- -000 ---- -000 ---- -uuu hdct0 --00 0000 --00 0000 --00 0000 --uu uuuu hdct1 --00 0000 --00 0000 --00 0000 --uu uuuu hdct ? --00 0000 --00 0000 --00 0000 --uu uuuu hdct ? --00 0000 --00 0000 --00 0000 --uu uuuu hdct4 --00 0000 --00 0000 --00 0000 --uu uuuu hdct5 --00 0000 --00 0000 --00 0000 --uu uuuu hdct6 --00 0000 --00 0000 --00 0000 --uu uuuu hdct7 --00 0000 --00 0000 --00 0000 --uu uuuu hdct8 --00 0000 --00 0000 --00 0000 --uu uuuu hdct9 --00 0000 --00 0000 --00 0000 --uu uuuu hdct10 --00 0000 --00 0000 --00 0000 --uu uuuu hdct11 --00 0000 --00 0000 --00 0000 --uu uuuu ? ptc1 0000 0000 0000 0000 0000 0000 uuuu uuuu ? ptc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 5c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- t ? 5c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 5dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 5dh 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 5al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 5ah 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 5rp 0000 0000 0000 0000 0000 0000 uuuu uuuu opacal -001 0000 -001 0000 -001 0000 -uuu uuuu dc ? cr0 0000 1010 0000 1010 0000 1010 uuuu uuuu dc ? cr1 ---0 0000 ---0 0000 ---0 0000 ---u uuuu
rev. 1.10 54 ? a ? ? 0 ? ? 01 ? rev. 1.10 55 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (idle) t ? 0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0dh ---- --00 ---- --00 ---- --00 ---- --uu t ? 0al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0ah ---- --00 ---- --00 ---- --00 ---- --uu t ? 1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1dh ---- --00 ---- --00 ---- --00 ---- --uu t ? 1al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1ah ---- --00 ---- --00 ---- --00 ---- --uu t ?? c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? dh ---- --00 ---- --00 ---- --00 ---- --uu t ?? al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? ah ---- --00 ---- --00 ---- --00 ---- --uu t ?? c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? dh ---- --00 ---- --00 ---- --00 ---- --uu t ?? al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? ah 0000 0000 0000 0000 0000 0000 uuuu uuuu note: - stands for not implement u stands for unchanged x stands for unknown
rev. 1.10 54 ?a? ?0? ?01? rev. 1.10 55 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? input/output ports holtek microcontrollers offe r consi derable fexi bility on the ir i/o ports. wi th the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. this device provide bidirectional input/output lines labeled with port names pa~pd these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d ? d ? d1 d0 papu d7 d6 d5 d4 d ? d ? d1 d0 pa d7 d6 d5 d4 d ? d ? d1 d0 pac d7 d6 d5 d4 d ? d ? d1 d0 pbpu d7 d6 d5 d4 d ? d ? d1 d0 pb d7 d6 d5 d4 d ? d ? d1 d0 pbc d7 d6 d5 d4 d ? d ? d1 d0 pcpu d7 d6 d5 d4 d ? d ? d1 d0 pc d7 d6 d5 d4 d ? d ? d1 d0 pcc d7 d6 d5 d4 d ? d ? d1 d0 pdpu d ? d ? d1 d0 pd d ? d ? d1 d0 pdc d ? d ? d1 d0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers, namely papu~pdpu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pbpu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0
rev. 1.10 56 ? a ? ? 0 ? ? 01 ? rev. 1.10 57 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? pcpu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 i/o port bit 7~bit 0 pull-high control pdpu register bit 7 6 5 4 3 2 1 0 name d ? d ? d1 d0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~0 port d bit 3~bit 0 pull-high control port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist t o wa ke-up t he m icrocontroller, one of whi ch i s t o c hange t he l ogic c ondition on one of t he port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu: port a bit 7~bit 0 wake-up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as pac~pdc, to control the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin.
rev. 1.10 56 ?a? ?0? ?01? rev. 1.10 57 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pbc register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pcc register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 i/o port bit 7~bit 0 input/output control pdc register bit 7 6 5 4 3 2 1 0 name d ? d ? d1 d0 r/w r/w r/w r/w r/w por 1 1 1 1 bit 7~4 unimplemented, read as 0 bit 3~0 i/o port bit 3~bit 0 input/output control 0: output 1: input
rev. 1.10 58 ? a ? ? 0 ? ? 01 ? rev. 1.10 59 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

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rev. 1.10 58 ?a? ?0? ?01? rev. 1.10 59 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the le vel of whic h depe nds on the othe r conne cted ci rcuitry and whet her pull -high selections have been chosen. if the port control registers, pac~pdc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data regist ers, pa~pd, are frst program med. sel ecting which pins are input s and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by pro gramming in dividual bi ts in th e por t co ntrol regi ster usi ng th e se t [m]. i an d clr [m].i instruct ions. note tha t when using the se bit cont rol inst ructions, a rea d-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.10 60 ? a ? ? 0 ? ? 01 ? rev. 1.10 61 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions each device includes several timer modules, abbreviated to the nam e tm. the tms are mul ti-purpose ti ming uni ts and serve to provi de operations such as timer/counter , input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either multiple interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact and standard tm sections. introduction the device contains fve tms having a reference name of tm0, tm1, tm2, tm3 and tm5. each individual tm can be cat egorised as a c ertain type , namel y com pact type tm, four 10-bit ctm and one 16-bit ctm. the main features are summarised in the accompanying table. function ctm timer/counter i/p capture compare ? atch output pw ? channels 1 single pulse output pw ? alignment edge pw ? adjustment period & dut ? dut ? or period tm function summary tm operation tm offer a dive rse range of funct ions, from sim ple ti ming opera tions to pwm signa l gene ration. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock sou rce whi ch dr ives th e ma in co unter in ea ch tm ca n or iginate fr om va rious sou rces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setting these bits to the value 101 will select an undefned clock input, in effect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact type tm has two inte rnal interrupts, one for each of the interna l comparat or a or comparator p, which generate a tm interrupt when a compare match condition occurs.
rev. 1.10 60 ?a? ?0? ?01? rev. 1.10 61 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected usi ng th e tn ck2~tnck0 bi ts. th e tm in put pi n ca n be ch osen to ha ve ei ther a rising or falling active edge. the tms each have two output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. all tm output pin names have a _n suffx. pin names that include a _0 or _1 suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. ctm0 ctm1 ctm2 ctm3 ctm5 tp0_0 ? tp0_1 tp1_0 ? tp1_1 tp ? _0 ? tp ? _1 tp ? _0 ? tp ? _1 tp5_0 ? tp5_1 tm output pins tm input/output pin control registers selecting to have a tm input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. registers bit 7 6 5 4 3 2 1 0 t ? pc0 t ? cp1 t ? cp0 t ? cp1 t ? cp0 t1cp1 t1cp0 t0cp1 t0cp0 t ? pc1 t5cp1 t5cp0 tm input/output pin control registers list tmpc0 register bit 7 6 5 4 3 2 1 0 name t ? cp1 t ? cp0 t ? cp1 t ? cp0 t1cp1 t1cp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t3cp1: tp3_1 pin control 0: disable 1: enable bit 6 t3cp0: tp3_0 pin control 0: disable 1: enable bit 5 t2cp1: tp2_1 pin control 0: disable 1: enable
rev. 1.10 6 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 6? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? bit 4 t2cp0: tp2_0 pin control 0: disable 1: enable bit 3 t1cp1: tp1_1 pin control 0: disable 1: enable bit 2 t1cp0: tp1_0 pin control 0: disable 1: enable bit 1 t0cp1: tp0_1 pin control 0: disable 1: enable bit 0 t0cp0: tp0_0 pin control 0: disable 1: enable tmpc1 register bit 7 6 5 4 3 2 1 0 name t5cp1 t5cp0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1 t5cp1: tp5_1 pin control 0: disable 1: enable bit 0 t5cp0: tp5_0 pin control 0: disable 1: enable programming considerations the tm counter registers and the capture/compare ccra is 10-bit or 16-bit register, have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer , reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low by te on ly ta kes pl ace whe n a wri te or re ad op eration to it s co rresponding hi gh by te is executed. data bus 8- bit buffer t?xdh t?xdl t?xah t?xal t? counter register ( read onl? ) t? ccra register ( read / write )
rev. 1.10 6? ?a? ?0? ?01? rev. 1.10 6 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? the following steps show the read and write procedures: ? writing data to ccra step 1. write data to low byte tmxal C note that here data is only written to the 8-bit buffer. step 2. write data to high byte tmxah C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra step 1. read data from the high byte tmxdh or tmxah C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. step 2. read data from the low byte tmxdl or tmxal C this step reads data from the 8-bit buffer. compact type tm C ctm although the simplest form of the tm types, the compact tm type still contains three operating modes, which ar e co mpare mat ch out put, ti mer/event co unter an d pwm out put mo des. th e compact tm can also be control led wit h an exte rnal input pin and can drive two exte rnal output pins. these two external output pins can be the same signal or the inverse signal.
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rev. 1.10 64 ? a ? ? 0 ? ? 01 ? rev. 1.10 65 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? compact tm operation at its core is a 10-bit or 16-bit count-up counte r whic h is driven by a user selec table inte rnal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits or eight bits in the counter while the ccra is the ten bits or sixteen bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit or 16-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. compact type tm register description overall operati on of the compact tm is cont rolled using six regist ers. a read only regist er pair exists to store the internal counter 10-bit or 16-bit value, while a read/write register pair exists to store the internal 10-bit or 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three or eight ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t ? nc0 tnpau tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 t ? nc1 tn ? 1 tn ? 0 tnio1 tnio0 tnoc tnpol tndpx tncclr t ? ndl d7 d6 d5 d4 d ? d ? d1 d0 t ? ndh d9 d8 t ? nal d7 d6 d5 d4 d ? d ? d1 d0 t ? nah d9 d8 10-bit compact tm register list(n=0, 1, 2, 3) name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t ? 5c0 t5pau t5ck ? t5ck1 t5ck0 t5on t5rp ? t5rp1 t5rp0 t ? 5c1 t5 ? 1 t5 ? 0 t5io1 t5io0 t5oc t5pol t5dpx t5cclr t ? 5dl d7 d6 d5 d4 d ? d ? d1 d0 t ? 5dh d15 d14 d1 ? d1 ? d11 d10 d9 d8 t ? 5al d7 d6 d5 d4 d ? d ? d1 d0 t ? 5ah d15 d14 d1 ? d1 ? d11 d10 d9 d8 t ? 5rp d7 d6 d5 d4 d ? d ? d1 d0 16-bit compact tm register list tmndl register(n=0, 1, 2, 3) 10-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl: tmn counter low byte register bit 7~bit 0 tmn 10-bit counter bit 7~bit 0
rev. 1.10 64 ?a? ?0? ?01? rev. 1.10 65 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? tmndh register(n=0, 1, 2, 3) 10-bit ctm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmndh: tmn counter high byte register bit 1~bit 0 tmn 10-bit counter bit 9~bit 8 tmnal register(n=0, 1, 2, 3) 10-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal: tmn ccra low byte register bit 7~bit 0 tmn 10-bit ccra bit 7~bit 0 tmnah register(n=0, 1, 2, 3) 10-bit ctm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmnah: tmn ccra high byte register bit 1~bit 0 tmn 10-bit ccra bit 9~bit 8 tm5dl register 16-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm5dl: tm5 counter low byte register bit 7~bit 0 tm5 16-bit counter bit 7~bit 0 tm5dh register 16-bit ctm bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm5dh: tm5 counter high byte register bit 7~bit 0 tm5 16-bit counter bit 15~bit 8
rev. 1.10 66 ? a ? ? 0 ? ? 01 ? rev. 1.10 67 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? tm5al register 16-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm5al: tm5 ccra low byte register bit 7~bit 0 tm5 16-bit ccra bit 7~bit 0 tm5ah register 16-bit ctm bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm5ah: tm5 ccra high byte register bit 8~bit 0 tm5 16-bit ccra bit 15~bit 8 tmnc0 register(n=0, 1, 2, 3) 10-bit ctm bit 7 6 5 4 3 2 1 0 name tnpau tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau: tmn counter pause control 0: run 1: pause the counter ca n be pause d by set ting thi s bit high. cle aring the bit to ze ro rest ores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0: select tmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: reserved 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm0. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 tnon: tmn counter on/of f control 0: off 1: on this bit controls the overall on/off function of the tmn. setting the bit high enables the counter to run, clearing the bit disables the tmn. clearing this bit to zero will stop the counter from counting and turn off the tmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal
rev. 1.10 66 ?a? ?0? ?01? rev. 1.10 67 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? counter will retain its residual value. if the tmn is in the compare match output mode then the tmn output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0: tmn ccrp 3-bit register , compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter s highest three bits. the result of this comparison ca n be sel ected to cl ear the int ernal count er if the tnc clr bit is set to zero. setting the tnccl r bit to zero ensures tha t a com pare ma tch wit h the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all thre e bit s to ze ro is in ef fect al lowing the count er to overfl ow at it s maximum value. tmnc1 register(n=0, 1, 2, 3) 10-bit ctm bit 7 6 5 4 3 2 1 0 name tn ? 1 tn ? 0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0: select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0: select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused
rev. 1.10 68 ? a ? ? 0 ? ? 01 ? rev. 1.10 69 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? these two bits are used to determine how the tmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tmn is running. in the compare mat ch output mode, the tnio1 and tnio0 bit s det ermine how the tmn output pin changes state when a compare match occurs from the comparator a. the tmn out put pin ca n be set up to swit ch hig h, swit ch low or to tog gle it s pre sent state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tmn output pin should be setup using the tnoc bit in the tmnc1 register. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tmn output pin when a compare match occurs. after the tmn output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is mo dified by ch anging th ese two bi ts. it is ne cessary to on ly ch ange th e values of the tnio1 and tnio0 bit s only aft er the tmn has bee n swit ched off. unpredictable pw m out puts wi ll oc cur i f t he tnio1 a nd tnio0 bi ts a re c hanged whe n the tm is running. bit 3 tnoc: tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tmn output pin. its operation depends upon whether tmn is being used in the compare match output mode or in the pwm mode. it has no effect if the tmn is in the timer/counter mode. in the compare match output mode it det ermines the logi c le vel of he tmn out put pin befo re a com pare match occurs. in the pwm mode it dete rmines if the pwm signal is act ive high or active low. bit 2 tnpol: tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tp0_1 output pin. when the bit is set high the tmn output pin will be inverted and not inverted when the bit is zero. it has no effect if the tmn is in the timer/counter mode. bit 1 tndpx: tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr: select tmn counter clear condition 0: tmn comparator p match 1: tmn comparator a match this bit is used to sel ect the me thod whic h cl ears the count er. rem ember tha t the compact tmn co ntains two com parators, com parator a an d com parator p, ei ther of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode.
rev. 1.10 68 ?a? ?0? ?01? rev. 1.10 69 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? tm5c0 register16-bit ctm bit 7 6 5 4 3 2 1 0 name t5pau t5ck ? t5ck1 t5ck0 t5on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 t5pau: tm5 counter pause control 0: run 1: pause the counter ca n be pause d by set ting thi s bit high. cle aring the bit to ze ro rest ores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t5ck2~t5ck0: select tm5 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: reserved 110: tck5 rising edge clock 111: tck5 falling edge clock these three bits are used to select the clock source for the tm5. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t5on: tm5 counter on/of f control 0: off 1: on this bit controls the overall on/off function of the tm5. setting the bit high enables the counter to run, clearing the bit disables the tm5. clearing this bit to zero will stop the counter from counting and turn off the tm5 which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tm5 is in the compare match output mode then the tm5 output pin will be reset to its initial condition, as specifed by the t5oc bit, when the t5on bit changes from low to high. bit 2~0 unimplemented, read as "0" tm5c1 register 16-bit ctm bit 7 6 5 4 3 2 1 0 name t5 ? 1 t5 ? 0 t5io1 t5io0 t5oc t5pol t5dpx t5cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t5m1~t5m0: select tm5 operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t5m1 and t5m0 bits. in the timer/counter mode, the tm output pin control must be disabled.
rev. 1.10 70 ? a ? ? 0 ? ? 01 ? rev. 1.10 71 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? bit 5~4 t5io1~t5io0: select tp5_0, tp5_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tm5 output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm5 is running. in the compare mat ch output mode, the t5io1 and t5io0 bit s det ermine how the tm5 output pin changes state when a compare match occurs from the comparator a. the tm5 out put pin ca n be set up to swit ch hig h, swit ch low or to tog gle it s pre sent state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm5 output pin should be setup using the t5oc bit in the tm5c1 register. note that the output level requested by the t5io1 and t5io0 bits must be different from the initial value setup using the t5oc bit otherwise no change will occur on the tm5 output pin when a compare match occurs. after the tm5 output pin changes state it can be reset to its initial level by changing the level of the t5on bit from low to high. in the pwm mode, the t5io1 and t5io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is mo dified by ch anging th ese two bi ts. it is ne cessary to on ly ch ange th e values of the t5io1 and t5io0 bit s only aft er the tm5 has bee n swit ched off. unpredictable pw m out puts wi ll oc cur i f t he t5io1 a nd t5io0 bi ts a re c hanged whe n the tm is running. bit 3 t5oc: tp5_0, tp5_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm5 output pin. its operation depends upon whether tm5 is being used in the compare match output mode or in the pwm mode. it has no effect if the tm5 is in the timer/counter mode. in the compare match output mode it det ermines the logi c le vel of he tm5 out put pin befo re a com pare match occurs. in the pwm mode it dete rmines if the pwm signal is act ive high or active low. bit 2 t5pol: tp5_0, tp5_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp5_0 or tp5_1 output pin. when the bit is set high the tm5 output pin will be inverted and not inverted when the bit is zero. it has no effect if the tmn is in the timer/counter mode. bit 1 t5dpx: tm5 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform.
rev. 1.10 70 ?a? ?0? ?01? rev. 1.10 71 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? bit 0 t5cclr: select tm5 counter clear condition 0: tm5 comparator p match 1: tm5 comparator a match this bit is used to sel ect the me thod whic h cl ears the count er. rem ember tha t the compact tm5 co ntains two com parators, com parator a an d com parator p, ei ther of which can be selected to clear the internal counter. with the t5cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t5cclr bit is not used in the pwm mode. tm5rp register C 16-bit ctm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm5 ccrp 8-bit register , compared with the tm5 counter bit 15~bit 8 comparator p match period 0: 1024 tmn clocks 1~255: 256(1~255) tm5 clocks these three bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counter s highest eight bits. the result of this comparison ca n be sel ected to cl ear the int ernal count er if the t5c clr bit is set to zero. setting the t5ccl r bit to zero ensures tha t a com pare ma tch wit h the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all thre e bit s to ze ro is in ef fect al lowing the count er to overfl ow at it s maximum value. compact type tm operating modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm mode or ti mer/counter mod e. th e op erating mo de is sel ected usi ng th e tn m1 an d tn m0 bits in the tmnc1 register . compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare ma tch oc curs fro m com parator p, th e ot her is whe n th e ccr p bi ts ar e al l ze ro whi ch allows the counter to overfow. here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively , will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, or 16-bit, ffff hex ,value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag
rev. 1.10 7 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 7? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? is generated aft er a com pare ma tch occ urs from com parator a. the tnpf int errupt reque st fla g, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in whi ch th e tm ou tput pi n ch anges sta te ar e de termined by th e co ndition of th e tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from compa rator a. the ini tial condi tion of the tm output pin, whic h is set up aft er the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. counter value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin time ccrp =0 ccrp > 0 counter overflow ccrp > 0 counter cleared b? ccrp value pause resume stop counter restart tncclr = 0 ; tn? [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag note tnio [1:0 ] = 10 active high output select here tnio [1:0 ] = 11 toggle output select output not affected b? tnaf flag . remains high until reset b? tnon bit output pin reset to initial value output controlled b? other pin - shared function output inverts when tnpol is high 0x? ff or 0 xffff compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=0, 1, 2, 3, 5
rev. 1.10 7? ?a? ?0? ?01? rev. 1.10 7 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? ccrp ccra 0x ? ff or 0xffff ccra = 0 counter overflows ccrp int. flag tnpf ccra int. flag tnaf ccra > 0 counter cleared b ? ccra value t ? o/p pin tnon bit pause counter reset output pin reset to initial value output pin set to initial level low if tnoc = 0 output toggle with tnaf flag here tnio1 ? tnio0 = 11 toggle output select now tnio1 ? tnio0 = 10 active high output select tnpau bit resume stop time tnpf not generated no tnaf flag generated on ccra overflow output does not change ccra = 0 output inverts when tnpol is high tnpol bit tncclr = 1; tn ? [1 ? 0] = 00 output controlled b ? other pin - shared function output not affected b ? tnaf flag remains high until reset b ? tnon bit counter value compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 5. n=0, 1, 2, 3, 5
rev. 1.10 74 ? a ? ? 0 ? ? 01 ? rev. 1.10 75 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/c ounter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating co ntrol, il lumination co ntrol et c. by pr oviding a sig nal of fi xed fre quency bu t of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is ext remely fle xible. in the pwm mode , the tncclr bit has no ef fect on the pwm operation. both of the ccra and ccrp regi sters are used to generat e the pwm waveform , one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. 10-bit ctm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 dut ? ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125 khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit ctm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra dut ? 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 the pwm ou tput pe riod is de termined by th e cc ra re gister va lue to gether wit h th e tm cl ock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.10 74 ?a? ?0? ?01? rev. 1.10 75 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? 16-bit ctm, pwm mode, edge-aligned mode, tndpx=0 ccrp 1~255 0 period ccrp ? 56 655 ? 6 dut ? ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=2 and ccra=128, the ctm pwm output freque ncy=(f sys /4)/(2256)=f sys /2048=7.8125 khz, duty=128/ (2256)=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 16-bit ctm, pwm mode, edge-aligned mode, tndpx=1 ccrp 1~255 0 period ccra dut ? ccrp ? 56 655 ? 6 the pwm ou tput pe riod is de termined by th e cc ra re gister va lue to gether wit h th e tm cl ock while the pwm duty cycle is defned by the (ccrp256) except when the ccrp value is equal to 0. counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin (tnoc=1) time counter cleared b? ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0; tn? [1:0] = 10 pw? dut? c?cle set b? ccra pw? resumes operation output controlled b? other pin-shared function output inverts when tnpol = 1 pw? period set b? ccrp t? o/p pin (tnoc=0) pwm mode C tndpx=0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0, 1, 2, 3, 5
rev. 1.10 76 ? a ? ? 0 ? ? 01 ? rev. 1.10 77 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin (tnoc=1) time counter cleared b? ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1; tn? [1:0] = 10 pw? dut? c?cle set b? ccrp pw? resumes operation output controlled b? other pin-shared function output inverts when tnpol = 1 pw? period set b? ccra t? o/p pin (tnoc=0) pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0, 1, 2, 3, 5 buzzer control buzzer ht45f??c 10-bit ct? t?? the 10-bit ctm can drive an external buzzer using its pwm mode to provide volume control.
rev. 1.10 76 ?a? ?0? ?01? rev. 1.10 77 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? capture timer module C captm the capture timer module is a timing unit specifically used for motor control purposes. the captm is controlled by a program selectable clock source and by three interrupt sources from the motor positioning hall sensors. capture timer overview at the core of the capture timer is a 16-bit count-up counter which is driven by a user selectable internal clock source which is some multiple of the system clock or by the pwm. there is also an internal comparator which compares the value of this 16-bit counter with a pre-programmed 16- bit value stored in two registers. there are two basic modes of operation, a compare mode and a capture mode, ea ch of whic h ca n be used to rese t the int ernal count er. wh en a com pare ma tch situation is reached a signal will be generated to reset the internal counter. the counter can also be cleared when a capture trigger is generated by the three external sources, int0a, int0b and int0c. noise filter x? rising/falling /double edge detector compare register capt?ah /capt?al compare capt?ch /capt?cl clear capture counter clr capt?_over capt?_cmp int0a int0b int0c caps1/caps 0 16-bit captm clk captck[?:0 ] pw?o f sys /? f sys /1?8 f sys /64 ha_int hb_int hc_int rising/falling /double edge detector ha hb hc capture timer block diagram capture timer register description overall operation of the capture timer is controlled using eight registers. a read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bi t c ompare va lue. an a dditional re ad onl y re gister pa ir i s use d t o st ore t he c apture va lue. the remaining two registers are control registers which setup the different operating and control modes.
rev. 1.10 78 ? a ? ? 0 ? ? 01 ? rev. 1.10 79 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 captc0 captpau captck ? captck1 captck0 capton caps1 caps0 captc1 capeg1 capeg0 capen capnft capnfs capfil capclr ca ? clr capt ? dl d7 d6 d5 d4 d ? d ? d1 d0 capt ? dh d15 d14 d1 ? d1 ? d11 d10 d9 d8 capt ? al d7 d6 d5 d4 d ? d ? d1 d0 capt ? ah d15 d14 d1 ? d1 ? d11 d10 d9 d8 capt ? cl d7 d6 d5 d4 d ? d ? d1 d0 capt ? ch d15 d14 d1 ? d1 ? d11 d10 d9 d8 capture timer register list captc0 register bit 7 6 5 4 3 2 1 0 name captpau captck ? captck1 captck0 capton caps1 caps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 captpau: captm counter pause control 0: run 1: pause the counter ca n be pause d by set ting thi s bit high. cle aring the bit to ze ro rest ores normal counter operation. when in a pause condition the captm will remain power up and continue to con sume powe r. the cou nter wil l ret ain it s resi dual val ue when this bit changes from low to high and resume counting from this value when the bit changes to a low value again bit 6~4 captck2~captck0: select captm counter clock 000: pwmo 001: f h /2 010: f h /4 011: f h /8 100: f h /16 101: f h /32 110: f h /64 111: f h /128 these three bits are used to select the clock source for the captm. the clock source f h is the high speed system oscillator. bit 3 capton: captm counter on/off control 0: off 1: on this bit controls the overall on/off function of the captm. setting the bit high enables the count er to run, cl earing the bit disa bles the captm. cle aring thi s bit to zero will stop the counter from counting and turn off the captm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. bit 2 unimplemented, read as "0" bit 1~0 caps1~caps0: capture source select 00: int0a 01: int0b 10: int0c 11: unused
rev. 1.10 78 ?a? ?0? ?01? rev. 1.10 79 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? captc1 register bit 7 6 5 4 3 2 1 0 name capeg1 capeg0 capen capnft capnfs capfil capclr ca ? clr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 capeg1~capeg0: defnes captm capture active edge 00: disabled captm capture 01: rising edge capture 10: falling edge capture 11: dual edge capture bit 5 capen: captm capture input control 0: disable 1: enable this bit enables/disables the captm capture input source. bit 4 capnft: defnes captm noise filter sample times 0: twice 1: 4 times the captm noise filter circuit requires sampling twice or 4 times continuously, when they are all the same, the signal will be acknowledged. the sample time is decided by capnfs. bit 3 capnfs: captm noise filter clock source select 0: t sys 1: 4t sys the clock source for capture timer module counter is provided by f sys or f sys /4. bit 2 capfil: captm capture input flter control 0: disable 1: enable this bit enables/disables the captm capture input flter. bit 1 capclr: captm counter capture auto-reset control 0: disable 1: enable this bit enables/disables the au tomatic rese t of the count er when the val ue in captmdl an d capt mdh ha ve be en tr ansferred in to th e ca pture re gisters captmcl and captmch. bit 0 camclr: captm counter compare match auto-reset control 0: disable 1: enable this bit enables/disables the automatic reset of the counter when the a compare match has occurred.
rev. 1.10 80 ? a ? ? 0 ? ? 01 ? rev. 1.10 81 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? captmdl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 captmdl: captm counter low byte register bit 7~bit 0 captm 16-bit counter bit 7 ~ bit 0 captmdh register bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 captmdh: captm counter high byte register bit 7~bit 0 captm 16-bit counter bit 15 ~ bit 8. captmal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 captmal: captm compare low byte register bit 7~bit 0 captm 16-bit compare register bit 7~bit 0. captmah register bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 captmah: captm compare high byte register bit 7~bit 0 captm 16-bit compare register bit 15~bit 8. captmcl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por x x x x x x x x "x"unknown bit 7~0 captmcl: captm capture low byte register bit 7~bit 0 captm 16-bit capture register bit 7~bit 0
rev. 1.10 80 ?a? ?0? ?01? rev. 1.10 81 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? captmch register bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r r r r r r r r por x x x x x x x x "x"unknown bit 7~0 captmch: captm capture high byte register bit 7~bit 0 captm 16-bit capture register bit 15~bit 8. capture timer operation the capture time r is used to detect and measure input signal pulse widths and a periods. it can be used in both a capture or compare mode. the timer inputs are the three capture inputs int0a, int0b and int0c. each of these capture inputs has its own edge detector selection, to choose between high, low or both edge trigger types. the capton bit is used to control the overall capture timer enable/disable function. disabling the capture module when not used will reduce the device power consumption. additionally the capture input control is enabled/disabled using the capen control bit. the trigger edge option are setup using the capeg1 and capeg0 bits, to select either positive edge, negative edge or both edges. capture mode operation the capture timer module contains 2 capture registers, captmcl and captmch, which are used to store the present value in the counter. when the capture module is enabled, then each time an external pin receives a valid trigger signal, the content of the free running 16-bit counter, which is contained in the captmdl and captmdh regi sters, will be capt ured int o the ca pture regi sters, captmcl and captmch. whe n thi s occ urs, the capof int errupt fla g bit in the int errupt control register wil l be set . if thi s int errupt is ena bled by set ting the int errupt ena ble bit , capoe, high, an interrupt will be generated. if the capclr bit is set high, then the 16-bit counter will be automatically reset after a capture event occurs. compare mode operation when the timer is used in the compare mode, the captmal and captmah registers are used to store the 16-bit compare value. when the free running value of the count-up 16-bit counter reaches a value equal to the progra mmed val ues in the se com pare regi sters, the capcf int errupt fag wil l be set which will generate an interrupt if its related interrupt enable bit is set. if the camclr bit is set high, th en th e co unter wil l be re set to ze ro au tomatically whe n a co mpare ma tch co ndition occurs. the rotor speed or a stalled motor condition can be detected by setting the compare registers to compare the captured signal edge transition time. if a rotor stall condition occurs, then a compare interrupt will be generated, after which the pwm motor drive circuit can be shut down to prevent a motor burn out situation. noise filter the timer also includes a noise filter which is used to flter out unwanted glitches or pulses on the trigger input pins. this function is enabled using the capfil bit. if the noise flter is enabled, the capture input signals must be sampled either 2 or 4 times, in order to recognize an edge as a valid capture event. the sampling 2 or 4 time units are based o either t sys or 4 t sys determined using the capnfs bit.
rev. 1.10 8 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 8? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? i/p o/p noise filter sampling noise filter with capnft and catnfs = 0 infrared receiver the device contains a function block to receive signals from infrared remote controls. these circuits assist with the implementation of integrated remote control functions for remote motor control. functional description the infrared receiver functional block contains a number of units to facilitate the implementation of infrared signal decoding such as ir code receiver circuit, noise flter, rmt capture circuit and rmte control. noise filter io ckt ir rx ckt ir tx :sc 5104 8- bitx? r?t r?t 0f r?tvf r?t 1f r?t 0 r?t 1 r?te _ ctl r?te ir _ rx block 10 -bit ct? ct? _ int rx_in rx_ int infrared receiver block diagram the external rx_in pin is connected to an internal flter to reduce the possibility of unwanted event counting events or inaccurate pulse width measurements due to adverse noise or spikes on the rx_ in input signal. in order to ensure that the ir code rx circuit and the motor control circuit works normally. the rmt capture circuit is implemented using two 8-bit rmt circuits, rmt0 and rmt1 registers to decode ir. as the ir code can be transmitted repeatedly, the rmte control circuit can make the decoding time short and reduce the effects which generated by the remote controlling on the motor controlling. the noise flt er ci rcuit is a i/o flt ering surge com pare whic h ca n flt er mi cro-second grade sharp-noise. antinoise pulse width maximum: (nf_vih[5:0]-nf_vil[5:0])5s
rev. 1.10 8? ?a? ?0? ?01? rev. 1.10 8 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? rmt timing noise filter a noise flter circuit is included to reduce the possibility of noise spikes or erroneous signal inputs being decoded as genuine inputs signals. dat_in dat_out noise filter dat_in dat_out nf_vih[4:0] nf_vil[4:0] noise filter noise filter registers description nf_vih register bit 7 6 5 4 3 2 1 0 name nf_byps d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 1 1 0 0 1 bit 7 nf_byps: bypass noise filter enable 0: disable 1: enable, dat_out=dat_in bit 6~5 unimplemented, read as "0" bit 4~0 nf_vih bit 4~bit 0 nf_vil register bit 7 6 5 4 3 2 1 0 name d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 bit 7~5 unimplement, read as "0" bit 4~0 nf_vil bit 4~bit0
rev. 1.10 84 ? a ? ? 0 ? ? 01 ? rev. 1.10 85 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? remote control timer C rmt the device cont ains two 8-bit rmt ti mer funct ions whic h are used for ir signa l dec oding. thi s function can be used to allow remote controllers to change the required motor operating mode. the remote control ti mer ca n det ect an edge tra nsition on the rx_in pin, aft er whic h thre e interrupt. signals can be generated. these are, rising edge interrupt signal, falling edge interrupt signal and a timer overflow interrupt signal. the control registers, rmt0 and rmt1, are used to store the captured data which measures the infrared input signal edge interval changes. the recorded data can then be used for ir decoding purposes. the application program can be used to decode the ir code frame data in the following ways: ? disabling the rmte when an ir da ta fr ame ha s be en de coded by th e pr ogram, th en th e rmt ca n be di sabled by th e following: rme=0 rmte=0. ? enabling the rmte use the 10-bit ctm as the ir decode scan restart mechanism to improve the motor control effciency. ? s/w mode: rme is set to high by the s/w . ? h/w mode: when a ctm_int is detected by the h/w (about 0.3s~1s) , then set rmte. note: f tbc is selected as the ctm clock source by s/w and adjusted using the tbc register . ct?_int/r?e_reg r?te r?e_reg 0.?sec~1sec hardware mode
rev. 1.10 84 ?a? ?0? ?01? rev. 1.10 85 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? rmt register description three registers are used for overall control of the remote control timer . a control register, rmtc, is used to setup the timer, while registers, rmt0 and rmt1, are used to store the decoded signal data. rmtc register bit 7 6 5 4 3 2 1 0 name r ? s1 r ? s0 r ? cs r ? e er ? tv er ? t1 er ? t0 r ? e ? s r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 rms1, rms0: selects the remote control timer clock 00: f x /2 5 01: f x /2 6 10: f x /2 7 11: f x /2 8 bit 5 rmcs: selects the remote control timer clock source f x 0: f sys /4 1: f sys bit 4 rme: controls the remote control timer 0: disable and clear counter to 0 1: enable and start counting bit 3 ermtv: controls the remote control timer overfow interrupt 0: disable 1: enable bit 2 ermt1: controls the remote control timer falling edge interrupt 0: disable 1: enable bit 1 ermt0: controls the remote control timer rising edge interrupt 0: disable 1: enable bit 0 rmems: rmte circuit mode select 0: s/w mode, rmte start circuit is defned by rme bit via s/w 1: h/w mode, rmte start circuit is defned by ctm interrupt via h/w rmt0 register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 rmt0: low level edge capture register bit 7~bit 0 rmt1 register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 rmt1: high level edge capture register bit 7~bit 0
rev. 1.10 86 ? a ? ? 0 ? ? 01 ? rev. 1.10 87 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding foll ow-on bene fts of lowe r cost s and reduc ed com ponent spac e requi rements. thi s device also includes some special a/d features for specifc use in motor control applications. a/d overview this device contains a 9-channel analog to digital converter, 8-channel can be directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 10-bit digital value. an additional channel is connected to the external current sense input pin, is, via an internal operational amplifier for signal amplification, before being transferred to the a/d converter input. a set of what are known as high and low boundary registers, allow the a/d converter digital output value to be compared with upper and lower limit values and a corresponding interrupt to be generated. an additional delay function allows a delay to be inserted into the pwm triggered a/d conversion start process to reduce the possibility of erroneous analog value sampling when the output power transistors are switching large motor currents. input channels a/d channel select bits input pins 9 acs ? ~acs0 an0~an7 ? is the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers. adrh adrl adhvdh adhvdl adlvdh adlvdl adchve adclve high boundar? value low boundar? value comparison t?pe control bits int _ ahl _ lim interrupt signal adc int _ ad _ eoc eocb bit compare converted value with upper and lower limits addl dela? register ?ux adsts bit start convert dela? time adstr bit pw? period interrupt signal pw? dut? interrupt signal ?ux pwis bit a/ d conversion start signal dlstr bit dela? on / off control programmable gain amplifier pb ?/is current sense pin input opavs 0 opavs ? gain control bits gain = x1/x5/x 10 /x ?0 acs?~acs0 pa?/an? pa5/an5 pa6/an6 pa7/an7 pa0/an0 pa1/an1 pa?/an? pa4/an4 ad hl / lv trigger a/d converter structure
rev. 1.10 86 ?a? ?0? ?01? rev. 1.10 87 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? a/d converter register description overall operation of the a/d converter is controlled using several registers. a read only register pair adrl/adrh exists to store the adc data 10-bit value. the adlvdl/adl vdh and adhvdl/ adhvdh registers are used to store the boundary limit values of the adc interrupt trigger while the addl regi ster is used to set up the sta rt conve rsion del ay ti me. the rem aining regi sters ar e control registers which setup the operating and control function of the a/d converter . register name bit 7 6 5 4 3 2 1 0 adrl d7 d6 d5 d4 d ? d ? d1 d0 adrh d9 d8 adcr0 adstr eocb adoff acs ? acs ? acs1 acs0 adcr1 adsts dlstr pwis adchve adclve adck ? adck1 adck0 ancsr0 pcr7 pcr6 pcr5 pcr4 pcr ? pcr ? pcr1 pcr0 ancsr1 pcr8 addl d7 d6 d5 d4 d ? d ? d1 d0 adlvdl d7 d6 d5 d4 d ? d ? d1 d0 adlvdh d9 d8 adhvdl d7 d6 d5 d4 d ? d ? d1 d0 adhvdh d9 d8 a/d converter register list a/d converter data registers C adrl, adrh as this device co ntains an in ternal 10- bit a/d co nverter, it re quires two da ta re gisters to sto re th e converted val ue. the se are a high byte regi ster, known as adrh, and a low byte regi ster, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. adrl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por x x x x x x x x "x"unknown bit 7~0 a/d low byte register bit 7~bit 0 adrh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por x x "x"unknown bit 7~2 unimplemented, read as "0" bit 1~0 a/d high byte register bit 1, bit 0
rev. 1.10 88 ? a ? ? 0 ? ? 01 ? rev. 1.10 89 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? a/d converter control registers C adcr0, adcr1, ancsr0, ancsr1, addl to control the function and operation of the a/d converter, four control registers known as adcr0, adcr1, ancsr0 and ancsr1 are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/d cl ock sou rce as wel l as co ntrolling th e sta rt fun ction an d mon itoring th e a/d converter end of conversion status. the acs3~acs0 bits in the adcr0 register defne the adc input channel number. as the device contains only one actual analog to digital converter hardware circuit, each of the individual 9 analog inputs must be routed to the converter. it is the function of the acs3~acs0 bits to determine which analog channel input pins or is pin is actually connected to the internal a/d converter . the ancsr0 and ancsr1 control registers contain the pcr8~pcr0 bits which determine which pins on port a or pb3 is used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input. the addl register exists to store the adc delay start time. adcr0 register bit 7 6 5 4 3 2 1 0 name adstr eocb adoff acs ? acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 bit 7 adstr: start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/d c onversion process. the bit is norm ally l ow but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb: end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running, the bit will be high. bit 5 adoff : adc module power on/of f control bit 0: adc module power on 1: adc module power of f this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the device power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 unimplemented, read as "0" bit 3~0 acs3 ~ acs0: select a/d channel 0000: an0 0001: an1
rev. 1.10 88 ?a? ?0? ?01? rev. 1.10 89 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000: is currrent sense input - via amplifer these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. adcr1 register bit 7 6 5 4 3 2 1 0 name adsts dlstr pwis adchve adclve adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adsts: select adc trigger circuit 0: select adstr trigger circuit 1: select delay trigger circuit bit 6 dlstr: delay start function control 0: disable but need to set addl to "0" 1: enable but need to set addl to non zero value bit 5 pwis: select pwm module interrupt source 0: select pwm period interrupt 1: select pwm duty interrupt bit 4~3 adchve~adclve: select adc interrupt trigger source 00: adlvd[9:0] < adr[9:0] < adhvd[9:0] 01: adr[9:0] <= adlvd[9:0] 10:adr[9:0] >= adhvd[9:0] 11: adr[9:0] <= adlvd[9:0] or adr[9:0] >= adhvd[9:0] bit 2~0 adck2~adck0: select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter .
rev. 1.10 90 ? a ? ? 0 ? ? 01 ? rev. 1.10 91 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? ancsr0 register bit 7 6 5 4 3 2 1 0 name pcr7 pcr6 pcr5 pcr4 pcr ? pcr ? pcr1 pcr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 pcr7: a/d input pin select 0: not a/d input 1: a/d input, an7 bit 6 pcr6: a/d input pin select 0: not a/d input 1: a/d input, an6 bit 5 pcr5: a/d input pin select 0: not a/d input 1: a/d input, an5 bit 4 pcr4: a/d input pin select 0: not a/d input 1: a/d input, an4 bit 3 pcr3: a/d input pin select 0: not a/d input 1: a/d input, an3 bit 2 pcr2: a/d input pin select 0: not a/d input 1: a/d input, an2 bit 1 pcr1: a/d input pin select 0: not a/d input 1: a/d input, an1 bit 0 pcr0: a/d input pin select 0: not a/d input 1: a/d input, an0 ancsr1 register bit 7 6 5 4 3 2 1 0 name pcr8 r/w r/w por 1 bit 7~1 unimplemented, read as "0" bit 0 pcr8: a/d input pin select 0: not a/d input 1: a/d input, is input, an8 addl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 adc delay-time register bit 7~bit 0 delay-time value (count by system clock)
rev. 1.10 90 ?a? ?0? ?01? rev. 1.10 91 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? a/d converter boundary registers C adlvdl, adlvdh, adhvdl, adhvdh the device contains what are known as boundary registers to store fxed values for comparison with the a/d converter converted value stored in adrl and adrh. there are two pairs of registers, a high boundary pair, known as adhvdl and adhvdh and a low boundary pair known as adlvdl and adlvdh. adlvdl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 adc low boundary low byte register bit 7~bit 0 adlvdh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 adc low boundary high byte register bit 1, bit 0 adhvdl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 adc high boundary low byte register bit 7~bit 0 adhvdh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 "x"unknown bit 7~2 unimplemented, read as "0" bit 1~0 adc high boundary high byte register bit 1~bit 0
rev. 1.10 9 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 9? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? a/d operation there are two ways to ini tiate an a/d convert er conve rsion cyc le, sel ected using the adsts bit . the frst of these is to use the adstr bit in the adcr0 register used to start and reset the a/d converter. when the microcontroller program sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the adstr bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. the second met hod of ini tiating a conve rsion is to uese the pwm int errupt signal. thi s can be sourced from either the pwm period or duty interrupt signal, selected using the pwis bit. the dlstr bit can activate a delay function which inserts a delay time between the incoming pwm interrupt signal and the actual start of the a/d conversion process, with the actual time being setup using the addl register . the actual delay time is calculated by the register content multiplied by the system clock period. the delay between the pwm interrupt and the start of the a/d conversion is to reduce the possibility of erroneous analog samples being taken during the time of large transient current switching by the motor drive transistors. note that if the dlstr bit selects no delay the addl register must be cleared to zero and vice-versa if the delay is selected, then a non-zero value must be programmed into the addl register . the eocb bit in the adcr0 regist er is used to indi cate when the analog to digit al conversion process is complete. this bit will be automatically set to zero by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt co ntrol re gister, an d if th e in terrupts ar e en abled, an ap propriate in ternal in terrupt signal will be generated. this a/d int ernal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/d clock source is determined by the system clocky, f sys , and by bits adck2~adck0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t adck , is 0.5s, care must be taken for system clock frequencies equal to or greater than 4mhz. for example, if the system cl ock operat es a t a frequenc y of 4mhz , t he adck2~adck0 bi ts should not be set to 0 00. doing so wil l gi ve a/d c lock pe riods th at are le ss th an th e mi nimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 5 ? hz ? 00ns* 400ns* 800ns v v v v 8qghqhg 10 ? hz 100ns* ? 00ns* 400ns* 800ns v v v 8qghqhg ? 0 ? hz 50ns* 100ns* ? 00ns* 400ns* 800ns v v 8qghqhg a/d clock period examples controlling the power on/of f funct ion of the a/d conve rter ci rcuitry is im plemented using the adoff bit in the adcr0 register. this bit must be zero to power on the a/d converter. even if no pins are selected for use as a/d inputs by clearing the pcr7~pcr0 bits in the ancsr0 register and pcr8 in the ancsr1 register, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used.
rev. 1.10 9? ?a? ?0? ?01? rev. 1.10 9 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? the boundary register pairs, adhvdl/adhvdh and adlvdl/adl vdh contain preset values which can be compared with the a/d converted values in the adrl/adrh registers. various types of comparisons can be made as defned by the adclve and adchve bits and an interrupt generated to inform the system that either the lower or higher boundary has been exceeded. this function can be used to ensure that the motor current operates within safe working limits. a/d input pins all of t he a/d a nalog i nput pi ns a re pi n-shared wi th the i/ o pi ns on port a a s we ll a s ot her funct ions. the pcr7~pcr0 bi ts in th e ancsr 0 re gister an d pcr8 bi t in th e ancsr 1 re gister, de termine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the pcr8~pcr0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way, pins can be changed under program co ntrol to ch ange th eir fu nction be tween a/d in puts an d ot her fu nctions. all pu ll- high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pac or pbc port control registers to enable the a/d input as when the pcr8~pcr0 bits enable an a/d input, the status of the port control register will be overridden. summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs3~acs0 bits which are also contained in the adcr0 register . ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the pcr7~pcr0 bits in the ancsr0 register and pcr8 in the ancsr1. ? step 5 select which trigger circuit is to be used by correctly programming the adsts bits in the adcr1. ? step 6 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bit, aeoce, must both be set high to do this. ? step 7 if the step 5 selects adstr trigger circuit, the analog to digital conversion process can be initialised by setting the adstr bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. if the step 5 selects pwm interrupt trigger delay circuit, the delay start function can be enabled by setting the dlstr bit in the adcr1 register. ? step 8 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0
rev. 1.10 94 ? a ? ? 0 ? ? 01 ? rev. 1.10 95 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? register can be polled. the conversion process is compl ete when this bit goes low . when this occurs the a/d data register adrl and adrh can be read to obtain the conversion value. as an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur . note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, du ring whi ch ti me the pr ogram ca n co ntinue wit h ot her fu nctions. the ti me ta ken fo r the a/d conversion is 16t adck where t adck is equal to the a/d clock period. 0 1 2 3 4 10 11 12 tdeoc adclk start eocb d[5:0] tdout adon tckl tckh tadc k tst tstart ton 000h toff a/d conversion timing programming considerations during microcontroller opera tions where the a/d conve rter is not bei ng used, the a/d int ernal circuitry can be switched off to reduce power consumption, by setting bit adoff high in the adcr0 register. wh en thi s ha ppens, th e in ternal a/d co nverter ci rcuits wil l no t co nsume po wer irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contains a 10-bit a/d converter, its full-scale converted digitised value is equal to 3ffh. since the full-scale analog input value is equal to the v dd voltage, this gives a single bit analog input value of v dd divided by 4096. 1 lsb=v dd 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value v dd 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converte r. except for the digit ised zero value , the subsequent digit ised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd level.
rev. 1.10 94 ?a? ?0? ?01? rev. 1.10 95 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ?

? ?? ? ? ? ?? ?
? ideal a/d transfer function a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst ex ample, th e me thod of pol ling th e eoc b bi t in th e adcr0 re gister is use d to de tect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr aeoce ; di sable ad c in terrupt mov a ,03h mov adcr1,a ; se lect f sys /8 as a/d clo ck clr adoff mov a,0fh ; se tup an csr0 an d an csr1 to con fgure pi ns an 0~an3 mov ancsr0,a mov a ,00h mov ancsr1,a mov a ,00h mov adcr0 ; en able and co nnect an 0 ch annel to a/ d co nverter : start_conversion: clr ad str ; hi gh pu lse on st art bit to in itiate co nversion set ad str ; re set a/ d clr ad str ; st art a/ d polling_eoc: sz eocb ; pol l th e ad cr0 re gister eo cb bit to de tect en d ; of a/ d co nversion jmp po lling_eoc ; co ntinue po lling mov a, adrl ; read lo w by te co nversion res ult va lue mov ad rl_buffer,a ; sa ve re sult to use r de fned re gister mov a, adrh ; read hi gh by te co nversion res ult va lue mov ad rh_buffer,a ; sa ve re sult to use r de fned re gister : : jmp start_conversion ; sta rt ne xt a/d co nversion example: using the interrupt method to detect the end of conversion clr mf1e ; di sable ad c in terrupt clr aeoce mov a ,03h
rev. 1.10 96 ? a ? ? 0 ? ? 01 ? rev. 1.10 97 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mov adcr1,a ; se lect f sys /8 as a/d clo ck clr adoff mov a,0fh ; se tup an csr0 an d an csr1 to con fgure pi ns an 0~an3 mov ancsr0,a mov a ,00h mov ancsr1,a mov a ,00h mov adcr0,a ; en able and co nnect an 0 ch annel to a/ d co nverter start_conversion: clr ad str ; hi gh pu lse on sta rt bit to in itiate co nversion set ad str ; re set a/ d clr ad str ; st art a/ d clr ae ocf ; cl ear ad c in terrupt req uest fa g set aeo ce ; ena ble ad c int errupt set mf 1e ; en able mu lti_interrupt 1 set em i ; ena ble glo bal int errupt : : ; adc interrupt service routine adc_isr: mov acc _stack,a ; sa ve ac c to us er de fned me mory mov a, status mov st atus_stack,a ; sa ve sta tus to use r de fned me mory : : mov a, adrl ; read lo w by te co nversion res ult va lue mov ad rl_buffer,a ; sa ve re sult to user de fned re gister mov a, adrh ; read hi gh by te co nversion res ult va lue mov ad rh_buffer,a ; sa ve re sult to user de fned re gister : : exit_int_isr: mov a, status_stack mov stat us,a ; r estore stat us fr om us er def ned me mory mov a, acc_stack ; re store ac c fro m us er de fned me mory reti
rev. 1.10 96 ?a? ?0? ?01? rev. 1.10 97 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? over-current detection the device contains an fully integrated over-current detect circuit which is used for motor protection. + _ opcm int _ is is opa : av =1/5/ 10 / 20 dac 8- bit opa comparator 0 int _ ad _ eoc int _ ahl _ lim adc adr eoc ad hl / lv trigger int trigger c0bpe adlvd / adhvd over-current detector block diagram over-current functional description the over-current functional block includes an amplifer, 10-bit a/d converter, 8-bit d/a converter and comparator. if an over-current situation is detected then the motor external drive circuit can be switched off immediately to prevent damage to the motor. two kinds of interrupts are generated which can be used for over-current detection. 1. a/d converter interrupt - int_ahl_lim 2. comparator 0 interrupt - int_is over-current register description there are three registers to control the function and operation of the over current detection circuits, known as opoms, opcm and opac al. the se 8-bi t reg isters defn e func tions such as th e opa operation mode selection, opa calibration and comparison. opcm is an 8-bit dac register used for opa comparison.
rev. 1.10 98 ? a ? ? 0 ? ? 01 ? rev. 1.10 99 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? opoms register bit 7 6 5 4 3 2 1 0 name c ? p0_eg1 c ? p0_eg0 opavs ? opavs1 opavs0 r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 bit 7~6 cmp0_eg1, cmp0_eg0: defnes comparator active edge 00: disable comparator 0 and dac0 01: rising edge 10: falling edge 11: dual edge bit 5~3 unimplemented, read as "0" bit 2~0 opavs2~opavs0: opa av mode select 000: disable opa 001: av=5 010: av=10 011: av=20 111: av=1 opcm register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 8-bit opa comparison register bit 7 ~ bit 0 opacal register bit 7 6 5 4 3 2 1 0 name ars aof ? aof4 aof ? aof ? aof1 aof0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 ars: comparator input offset calibration reference select 0: comparator negative input 1: comparator positive input bit 5 aofm: normal or calibration mode select 0: opamp or comparator mode 1: offset calibration mode bit 4~0 aof4~aof0: comparator input offset voltage calibration control 00000: minimum 10000: center 11111: maximum
rev. 1.10 98 ?a? ?0? ?01? rev. 1.10 99 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? linear hall sensor detection the motor position is detected using hall sensors for which the device includes circuitry to process signals from these sensors. int _ ad _ eoc int _ ahl _ lim adc hb adr eoc ad hl / lv trigger 8 bit dac + _ comparator 1 int _ hbdet ha hc hacm int trigger c1bpe adlvd / adhvd acs [3:0] hall sensor detector block diagram hall sensor detection function description the signals from the external linear hall sensors are monitored using the internal 8-bit dac, the internal 10-bit adc and internal comparator 1. the motor position is monitored by two interrupts int_hbdet or int_ahl_lim which are enabled/ disabled by the lhmc and hacm registers. the six step rotational change of state of the motor position can be tracked by setting the dac data and the lhmc register, to control the motor direction and speed, as shown in the fgure. sha shb shc 4v 2.5v 1v hl/hb s1 s2 s3 s4 s5 s6 s1 s2 s3 linear hall sensor output
rev. 1.10 100 ? a ? ? 0 ? ? 01 ? rev. 1.10 101 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? linear hall sensor control register description the lhmc is the linear hall sensor mode control register and the hacm is the 8-bit dac register for linear hall sensor comparison. lhmc register bit 7 6 5 4 3 2 1 0 name c ? p1_eg1 c ? p1_eg0 c1bpe c0bpe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~4 cmp1_eg1, cmp1_eg0: defnes comparator active edge 00: disable comparator 1 and dac1 01: rising edge 10: falling edge 11: dual edge bit 3~2 unimplemented, read as "0" bit 1 c1bpe: comparator 1 interrupt bypass(test option) 0: disable comparator 1 interrupt 1: enable comparator 1 interrupt bit 0 c0bpe: comparator 0 interrupt bypass(test option) 0: disable comparator 0 interrupt 1: enable comparator 0 interrupt hacm register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 8-bit linear hall sensor comparison register bit 7 ~ bit 0
rev. 1.10 100 ?a? ?0? ?01? rev. 1.10 101 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? bldc motor control circuit this sections describes how the device can be used to control brushless dc motors, otherwise known as bldc motors. its high level of functional integration and fexibility offer a full range of driving features for motor driving. functional description the pwm c ounter ci rcuit ou tput pwmo i s ha s an ad justable pwm du ty to co ntrol th e ou tput mo tor power thus controlling the motor speed. changing the pwm frequency can be used to enhance the motor drive effciency or to reduce noise and resonance generated during physical motor operation. the internal mas k circuit is used to determine which pwm modulation signals are enabled or disabled for the motor speed control. the pwm modulation signal can be output both the upper arms, gat/gbt/gct and the lower arms, gab/gbb/gcb, of the external gate driver transistor pairs under software control. the dead-time insertion circuit is used to ensure the upper and lower gate driver transistor pairs are not enabled simultaneously to prevent the occurrence of a virtual power short circuit. the dead time is selected under software control. the staggered circuit can force all the outputs to an off status if the software detects an error condition which could be due to externa l factors such as esd problems or both upper and lower external gate dri ver tr ansistor pa irs be ing sim ultaneously on . th e pol arity ci rcuit ca n sel ect th e output polarity of the bldc motor output control port to support many different types of external mos gate drive device circuit combinations. the motor protect circuit includes many detection circuits for functions such as a motor stall condition, over current protection, external edge triggered pause pin, external level trigger fault pin etc. the hall sensor decoder circuit is a six-step system which can be used control the motor direction. twelve re gisters, ea ch usi ng 6 bi ts, a re use d t o c ontrol t he di rection o f t he m otor. the m otor forwa rd, backward, brake and free functions are controlled by the hdcd/hdcr registers. the ha/hb/hc or sha/shb/shc can be selected as the hall sensor decoder circuit inputs. v v gat gab gbt gbb gct gcb ir?101 x? gate driver ht45f??c ?at ?ab ?bt ?bb ?ct ?cb v cc? pb?/is int0a int0b int0c fault pause
rev. 1.10 10 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 10? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? bldc application circuit 10-bit pwm counter ckt pwmr fpwm pwmo pwmp_int pwmd_int mptc1 mask gat gab gbt gbb gct gcb fault over current protection stall protection s/w pause pwmb mcf dts pwmc dutr prdr plc hdcd hc hb ha sha shb shc sa sb sc hdms 0 1 hall sensor dcoder 12x6 register hdcr frs brke motor protect ckt hat hab hbt hbb hth hcb protect hd_en pwm complement polarity dead time insert stall circuit at2 ab2 bt2 bb2 ct2 cb2 at0 ab0 bt0 bb0 ct0 cb0 at1 ab1 bt1 bb1 ct1 cb1 brke mcd mptc2 hall noise filter hall delay ckt hchk_num hnf_msel ctm16-int hdly_msel ctm_sel[1:0] bldc motor control block diagram pwm counter control circuit the device includes a 10-bit pwm generator. the pwm signal has both adjustable duty cycle and frequency that can be setup by programming 10-bit values into the corresponding pwm registers. 10-bit pwm counter ckt pwmr f pwm pwmo pwmp_int pwmd_int pwmc dutr prdr pwm block diagram
rev. 1.10 10? ?a? ?0? ?01? rev. 1.10 10 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? pwm register description overall pwm operation is controlled by a series of registers. the dutrl/dutrh register pair is used for pwm duty control for adjustment of the motor output power. the prdrl/prdrh register pair are used together to form a 10-bit value to setup the pwm period for pwm frequency adjustment. bei ng abl e to cha nge the pwm freque ncy is useful for mot or cha racteristic ma tching for problems such as noise reduction and resonance. the pwmrl/pwmrh registers are used to monitor the pwm counter dynamically . the pwmon bit in the pwmc register is the 10-bit pwm counter on/off bit. the pwm clock source for the pwm counter can be selected by pcks1~pcks0 bits in the pwmc register. it should be noted that the order of writing data to pwm register is msb. pwmc register bit 7 6 5 4 3 2 1 0 name pcks1 pcks0 pw ? on gatsel r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~4 pcks1, pcks0: clock source of the pwm counter select 000: f pwm , pwm frequency min.=20khz, f pwm base on 20mhz 001: f pwm /2, pwm frequency min.=10khz 010: f pwm /4, pwm frequency min.=5khz 011: f pwm /8, pwm frequency min.=2.5khz bit 3 pwmon: pwm circuit on/off control 0: off 1: on this bit controls the overall on/off function of the pwm. setting the bit high enables the counter to run, clearing the bit disables the pwm. clearing this bit to zero will stop the counter from cou nting and tu rn off th e pwm whic h wil l red uce it s powe r consumption. bit 2~1 unimplemented, read as "0" bit 0 gatsel: gate driver output select 0: gat/gab/gbt/gbb/gct/gcb are used for gate driver output pins 1: gat/gab/gbt/gbb/gct/gcb are used as pc[5:0] dutrl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 10-bit pwm duty register low byte register bit 7 ~ bit 0 10-bit dutr register bit 7 ~ bit 0
rev. 1.10 104 ? a ? ? 0 ? ? 01 ? rev. 1.10 105 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? dutrh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 10-bit pwm duty register high byte register bit 1 ~ bit 0 10-bit dutr register bit 9 ~ bit 8 prdrl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 10-bit pwm period register low byte register bit 7~bit 0 10-bit prdr register bit 7 ~ bit 0 prdrh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 pwm period high byte register bit 1~bit 0 10-bit dutr register bit 9 ~ bit 8 pwmrl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 10-bit pwm counter register low byte register bit 7~bit 0 10-bit pwm counter bit 7 ~ bit 0 pwmrh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 10-bit pwm counter register high byte register bit 1 ~ bit 0 pwm 10-bit counter bit 9 ~ bit 8
rev. 1.10 104 ?a? ?0? ?01? rev. 1.10 105 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mask function the device includes a motor control mask function for increased control fexibility. polarit? pw?b ir ?101 x? gate driver ?at ?ab ?bt ?bb ?ct ?cb pw?o hall sensor decoder 1? x 6 hat / hab / hbt / hbb / hct / hcb ?ask gat gab gbt gbb gct gcb ?cf dts plc dead time insert staggered circuit at ? ab? bt ? bb? ct ? cb ? at 0 ab0 bt 0 bb0 ct 0 cb 0 at 1 ab1 bt 1 bb1 ct 1 cb 1 ?cd brke p rotect mask function block diagram ?otor u v w power ?os ?oto hv ?at ?bt ?ct ?ab ?bb ?cb mask switching functional description the internal mask circuit has three operation modes, which are known as the normal mode, brake mode and motor protect mode. ? normal mode in the norma l mode, the mot or spee d cont rol me thod is det ermined by the pwms/ mpwe bit s in the mcf register. when pwms =0, the bottom port pwm output selects transistor pair bottom arm gab/ gbb/ gcb. when pwms =1, the top port pwm output selects transistor pair top arm, gab/ gbb/ gcb. when mpwe =0, the pwm output is disabled and at0/bt0/ct0/ab0/bb0/cb0 are all on. when mpwe =1, the pwm output is enabled and at0/bt0/ct0/ab0/bb0/cb0 can output a variable pwm signal for speed control. when mpwms=0, the pwm has a complementary output when mpwms=1, the pwm has a non-complementary output
rev. 1.10 106 ? a ? ? 0 ? ? 01 ? rev. 1.10 107 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? complementary control, mpwms=0 pw ? s=0 hat hab at0 ab0 pw ? s=1 hat hab at0 ab0 0 0 0 0 0 0 0 0 0 1 pw ? b pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o pw ? b 1 1 0 0 1 1 0 0 pw ? s=0 hbt hbb bt0 bb0 pw ? s=1 hbt hbb bt0 bb0 0 0 0 0 0 0 0 0 0 1 pw ? b pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o pw ? b 1 1 0 0 1 1 0 0 pw ? s=0 hct hcb ct0 cb0 pw ? s=1 hct hcb ct0 cb0 0 0 0 0 0 0 0 0 0 1 pw ? b pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o pw ? b 1 1 0 0 1 1 0 0 non-complementary control, mpwms=1 pw ? s=0 hat hab at0 ab0 pw ? s=1 hat hab at0 ab0 0 0 0 0 0 0 0 0 0 1 0 pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o 0 1 1 0 0 1 1 0 0 pw ? s=0 hbt hbb bt0 bb0 pw ? s=1 hbt hbb bt0 bb0 0 0 0 0 0 0 0 0 0 1 0 pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o 0 1 1 0 0 1 1 0 0 pw ? s=0 hct hcb ct0 cb0 pw ? s=1 hct hcb ct0 cb0 0 0 0 0 0 0 0 0 0 1 0 pw ? o 0 1 0 1 1 0 1 0 1 0 pw ? o 0 1 1 0 0 1 1 0 0 ? brake mode the brake mode has the highest priority. when activated, the external gate driver transistor pair top arm will be off and the bottom arm will be on. the brake truth decode table is shown below . brke=1 at0 bt0 ct0 ab0 bb0 cb0 1 0 0 0 0 1 1 1 d9 d8 ? motor protect mode when the motor prot ect mode is ac tivated, the ext ernal gat e drive r tra nsistor pai r ca n sel ect the brake, where the top arm is off and the bottom arm is on, or select free running where the top and
rev. 1.10 106 ?a? ?0? ?01? rev. 1.10 107 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? bottom arm are both off. the protection decode table is shown below . protect =1 gat gbt gct gab gbb gcb f ? os=0 0 0 0 0 0 0 f ? os=1 0 0 0 1 1 1 for 6-step communication, if the u winding and w winding are on then turn of f the v winding. if gat =1 and gab =0, turn on the u winding if gbt =0 and gbb =0, turn of f the v winding. if gct=pwmd and gcb=pwm, turn on the w winding and adjust the output power of the motor using the dutr register to control the speed. ht 45 f? ?c ?at ?ab ? bt ? bb ?ct ?cb ir ?10 1x? gat gab gbt gbb gct gcb drive signal block diagram v v u v w moto hv mat mbt mct mab mbb mcb moto hv moto hv 1 0 0 0 pwmd pwm current direction motor motor winding connection
rev. 1.10 108 ? a ? ? 0 ? ? 01 ? rev. 1.10 109 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? register description the device has two registers connected with the mask function control. these are the mcf register which is used for control and the mcd register which is used to read the status of the gate driver outputs. mcf register bit 7 6 5 4 3 2 1 0 name ? pw ? s ? pwe f ? os pw ? s r/w r/w r/w r/w r/w por 0 1 0 0 bit 7~4 unimplemented, read as "0" bit 3 mpwms: mask pwm mode select 0: complementary 1: non-complementary bit 2 mpwe: pwm output control 0: pwm output disable (at0/bt0/ct0/ab0/bb0/cb0 can not output pwm) 1: pwm output enable (at0/bt0/ct0/ab0/bb0/cb0 can output pwm to control speed) bit 1 fmos: fault mask output select 0: at0/bt0/ct0=0, ab0/bb0/cb0=0 1: at0/bt0/ct0=0, ab0/bb0/cb0=1 bit 0 pwms: top port/bottom port pwm select 0: select bottom port pwm output 1: select top port pwm output
rev. 1.10 108 ?a? ?0? ?01? rev. 1.10 109 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mcd register bit 7 6 5 4 3 2 1 0 name gat gab gbt gbb gct gcb r/w r r r r r r por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 gat/gab/gbt/gbb/gct/gcb: gate diver output monitor other functions several other functions exist for additional motor control drive signal fexibility. these are the dead time function, staggered function and polarity function. polarity pwmb ir2101x3 gate driver mat mab mbt mbb mct mcb pwmo hall sensor decoder 12x6 hat/ hab/ hbt/ hbb/ hct/ hcb mask gat gab gbt gbb gct gcb mcf dts plc dead time insert stagger ed circuit at2 ab2 bt2 bb2 ct2 cb2 at0 ab0 bt0 bb0 ct0 cb0 at1 ab1 bt1 bb1 ct1 cb1 mcd brke protect dead time, staggered and polarity function block diagram dead time function during transistor pair switching, the dead time function is used to prevent both upper and lower transistor pairs from conducting at the same time thus preventing a virtual short circuit condition from occurring. the actual dead time value can be setup to be within a value from 0.3s to 5s which is selected by the application program. the dead time insertion circuit requires six independent output circuits: ? when the at0/ab0/bt0/bb0/ct0/cb0 outputs experience a rising edge, then a dead time is inserted. ? when the at0/ab0/bt0/bb0/ct0/cb0 outputs experience a falling edge, then the outputs remain unchanged. the dead-time insertion circuit is only during motor control. the dead time function is enabled/ disabled by the dte bit in the dts register.
rev. 1.10 110 ? a ? ? 0 ? ? 01 ? rev. 1.10 111 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? . at0,ab0,bt0,bb0,ct0,cb0 dead-time insertion dead-time insertion dead-time insertion dead-time insertion 1.rising add dead-time insertion 2.falling unchange at1,ab1,bt1,bb1,ct1,cb1 dead time insertion timing a single register , dts, is dedicated for use by the dead time function. dts register bit 7 6 5 4 3 2 1 0 name dtcks1 dtcks0 dte d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 dtcks1, dtcks0 : dead-time clock source selection 00: f dt is f sys , f sys based on 20mhz 01: f dt is f sys /2 10: f dt is f sys /4 11: f dt is f sys /8 bit 5 dte: dead-time enable 0: dead-time=0 1: dead-time = (dts[4:0]+1)/f dt bit 4~0 d4~d0: dead-time register bit 4 ~ bit 0 dead-time counter. 5-bit dead-time value bits for dead-time unit. dead-time = (dts[4:0]+1)/f dt staggered function the staggered function is used to force all output drive transis tors to an off condition when a software error occurs or due to external factors such as esd. at1 ab1 at2 ab2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 the default condition for the bldc motor control circuit is designed for default n-type transistor pairs. this means a 1 value will switch the transistor on and a 0value will switch it of f.
rev. 1.10 110 ?a? ?0? ?01? rev. 1.10 111 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? polarity function this function allows setup of the external gate drive transistor on/off polarity status. a single register, plc, is used for overall control. plc register bit 7 6 5 4 3 2 1 0 name pcbc pctc pbbc pbtc pabc patc r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 pcbc: c pair bottom port gate output inverse control bit 4 pctc: c pair top port gate output inverse control bit 3 pbbc: b pair bottom port gate output inverse control bit 2 pbtc: b pair top port gate output inverse control bit 1 pabc: a pair bottom port gate output inverse control bit 0 patc: a pair top port gate output inverse control bit value status 0 output not inverted 1 output inverted plc register values note that the default output pin gat/gab/gbt/gbb/gct/gcb status is high impedance. hall sensor decoder this device contains a fully integrated hall sensor decoder function which interfaces to the hall sensors in the bldc motor for directional and speed control. hall sensor dcoder 12x6 regsietr hdcd hc hb ha sha shb shc sa sb sc hdms hdcr frs brke hat hab hbt hbb hct hcb mask at0 ab0 bt0 bb0 ct0 cb0 0 1 hdcen pwmo pwmb brke protect hall noise filter hall delay ckt hchk_num hnf_msel ctm-int x3 hdly_msel ctm_sel[1:0] hall sensor decoder block diagram the hall sensor input signals are selected by setting the hdms bit high. if the hdms bit is zero then sha/shb/shc will be used instead of the actual hall sensor signals.
rev. 1.10 11 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 11 ? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? hall sensor noise filter this device in cludes a hal l noi se fil ter fu nction to flt er ou t th e ef fects of no ise ge nerated by th e large switching currents of the motor driver. this generated noise may affect the hall sensor inputs (ha/hb/hc), which in turn may result in incorrect hall sensor output decoding. several registers are used to control the noise flter. the hnf_en bit in the hnf_msel register is used as the overall enable/disable bit for the noise flter. hnf_en bit status 0 noise filter off C ha/hb/hc not used 1 noise filter on hall sensor noise filter enable the sampling frequency of the hall noise flter is setup using the hfr_sel [3:0] bits. the hck_num [4:0] bits are used to setup the hall sensor input compare numbers. hck_num [4:0] sampling space = anti-noise ability = hall delay-t ime. it should be noted that longer hall delay times will result in higher rotor speed feedback signal distortion. hall sensor delay function the hall sensor function in the device includes a hall delay function which can implement a signal phase forward or phase backward operation. the following steps, which should be executed before the hall decoder is enabled, show how this function is activated. ? step 1 set the hall decode table to select either the phase forward or phase backward function. ? step 2 select which ctm is used to generate the delay time and set the selected ctm to run in the compare match mode by programming the ctm_sel1~ctm_sel0 bits. ? step 3 use the hdly_msel bit to select the hall delay circuit operating mode. the default value of hdly_msel is zero which will disable the hall delay circuit. if the hdly_msel bit is set high, then the hall delay circuit will be enabled. ? step 4 enable the hall decoder using the hdcen bit. the following points should be noted regarding the hdly_msel bit. when this bit is low, buf1[2:0] and buf2[2:0] will be cleared to zero. when this bit is low, tm0/tm1/tm5 retain their original tm functions. when the bit is high, the ctm which is selected by the delay function will be dedicated for use by the hall delay circuit. the original tm functions will still remain active except for the tnon bit which will be controlled automatically by the hardware.
rev. 1.10 11 ? ?a? ?0? ?01? rev. 1.10 11 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? with regard to the tm functions the following steps should be taken before the delay function is enabled. 1. keep tnon and tnpau = 0 2. the tm should be setup in the compare match mode 3. tncclr=1, therefore the tm is cleared with a comparator a match condition. 4. setup the delay time using tmna and tnckx. after the delay function is enabled, hdly_msel will change from low to high. the delay time must not be more than one step time of the hall input, which has six steps, otherwise the output can not be anticipated, will drop out of step. hall sensor decoder 1?x6 register buf?[?:0] buf1[?:0] d d d ct?-16 (t?5) ct?-10 (t?0) ct?-10 (t?1) hall noise filter hdcd ha hb hc hdly_?sel hat hab hbt hbb hct hcb ct?_sel[1:0] sha shb shc hd?s hall delay circuit hdcen ha0 hb0 hc0 ha1 hb1 hc1 ha? hb? hc? sa sb sc delay function block diagram ha0 hb0 hc0 sa sb sc delay time delay function timing
rev. 1.10 114 ? a ? ? 0 ? ? 01 ? rev. 1.10 115 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? motor control drive signals the direction of the bldc mot or is cont rolled using the hdcr, hdcd regi sters and a set of six hdct registers, hdct0~hdct11. when using the hall sensor decoder function, the direction can be determined using the frs bit and the brake can be controlled using the brke bit. both bits are in the hdcr register. six bits in the hdct0~hdct5 registers are used for the motor forward table, and six bits in the hdct6~hdct11 registers are used for the motor backward table. the accompanying tables show the truth tables for each of the registers. forward (hdcen=1 ? frs=0 ? brke=0) 60 degree 120 degree bit5 bit4 bit3 bit2 bit1 bit0 sa sb sc sa sb sc hat hab hbt hbb hct hcb 1 0 0 1 0 0 hdct0[5:0] 1 1 0 1 1 0 hdct1[5:0] 1 1 1 0 1 0 hdct ? [5:0] 0 1 1 0 1 1 hdct ? [5:0] 0 0 1 0 0 1 hdct4[5:0] 0 0 0 1 0 1 hdct5[5:0] hall sensor decoder forward truth table backward (hdcen=1 ? frs=1 ? brke=0) 60 degree 120 degree bit5 bit4 bit3 bit2 bit1 bit0 sa sb sc sa sb sc hat hab hbt hbb hct hcb 1 0 0 1 0 0 hdct6[5:0] 1 1 0 1 1 0 hdct7[5:0] 1 1 1 0 1 0 hdct8[5:0] 0 1 1 0 1 1 hdct9[5:0] 0 0 1 0 0 1 hdct10[5:0] 0 0 0 1 0 1 hdct11[5:0] hall sensor decoder backward truth table the truth tables for the brake function, hall decoder disable function and hall decoder error function are also shown below. brake (brke=1 ? hdcen=x ? frs=x) 60 degree 120 degree bit5 bit4 bit3 bit2 bit1 bit0 sa sb sc sa sb sc hat hab hbt hbb hct hcb v v v v v v 0 1 0 1 0 1 brake truth table hall decoder disable (hdcen=0) 60 degree 120 degree bit5 bit4 bit3 bit2 bit1 bit0 sa sb sc sa sb sc hat hab hbt hbb hct hcb v v v v v v 0 0 0 0 0 0 hall decoder disable truth table hall decoder error (hdcen=x) 60 degree 120 degree bit5 bit4 bit3 bit2 bit1 bit0 sa sb sc sa sb sc hat hab hbt hbb hct hcb 1 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 hall decoder error truth table
rev. 1.10 114 ?a? ?0? ?01? rev. 1.10 115 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? the relationship between the data in the truth tables and how they relate to actual motor drive signals is shown in th e ac companying ti ming dia gram. the ful l 6 ste p cyc le for bot h forwa rd and backward motor rotation is provided. s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 hat s a s b sc hall sensor : 120 degree motor forward n s ha hb hc ?- pole ?otor motor u v w moto hv mat mbt mct mab mbb mcb ?bt ?bb ?ct ?cb ?at ?ab ht 45 fm 2c ir 2101 x3 hbt hct hbb hcb hab motor drive signal timing diagram - forward direction s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s a s b sc hall sensor : 120 degree motor backward n s ha hb hc ?- pole ?otor motor u v w moto hv mat mbt mct mab mbb mcb ?bt ?bb ?ct ?cb ?at ?ab ht 45 fm 2c ir 2101 x3 hat hbt hct hbb hcb hab motor drive signal timing diagram - backward direction
rev. 1.10 116 ? a ? ? 0 ? ? 01 ? rev. 1.10 117 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? hall sensor decoder register description the hdcr register is the hall sensor decoder control register, hdcd is the hall sensor decoder input data register, and hdct0~hdct11 are the hall sensor decoder tables. the hchk_num register is the hall noise filter check number register and hnf_msel is the hall noise filter mode select register hdcr register bit 7 6 5 4 3 2 1 0 name ct ? _sel1 ct ? _sel0 hdly_ ? sel hals hd ? s brke frs hdcen r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7~6 ctm_sel1~ctm_sel0: ctm timer select of the hall delay circuit 00:tm5(16-bit ctm) 01:tm0(10-bit ctm) 10:tm1(10-bit ctm) 11:unused bit 5 hdly_msel: hall delay circuit select 0: select original path 1: select hall delay circuit bit 4 hals: hall sensor decoder mode select 0: hall sensor 60 degree 1: hall sensor 120 degree bit 3 hdms: hall sensor decoder mode select 0: s/w mode 1: hall sensor mode bit 2 brke: motor brake control 0: gat/gbt/gct/gab/gbb/gcb=v 1: gat/gbt/gct=0, gab/gbb/gcb=1 bit 1 frs: motor forward/backward select 0: forward 1: backward bit 0 hdcen: hall sensor decoder enable 0: disable 1: enable hdcd register bit 7 6 5 4 3 2 1 0 name shc shb sha r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as "0" bit 2 shc: s/w hall c bit 1 shb: s/w hall b bit 0 sha: s/w hall a
rev. 1.10 116 ?a? ?0? ?01? rev. 1.10 117 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? hdct11~0 register bit 7 6 5 4 3 2 1 0 name hatd habd hbtd hbbd hctd hcbd r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 hatd: gat output state control bit 4 habd: gab output state control bit 3 hbtd: gbt output state control bit 2 hbbd: gbb output state control bit 1 hctd: gct output state control bit 0 hcbd: gcb output state control bit value status 0 output is low 1 output is high output status hchk_num register bit 7 6 5 4 3 2 1 0 name hck_n4 hck_n ? hck_n ? hck_n1 hck_n0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as "0" bit 4~0 hck_n4~hck_n0: hall noise filter check number hnf_msel register bit 7 6 5 4 3 2 1 0 name hnf_en hfr_sel ? hfr_sel1 hfr_sel0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3 hnf_en: hall noise flter enable 0: disable(bypass) 1: enable bit 2~0 hfr_sel2~hfr_sel0: hall noise flter clock source select 000:f sys /2 001:f sys /4 010:f sys /8 011:f sys /16 100:f sys /32 101:f sys /64 110:f sys /128 111:unused
rev. 1.10 118 ? a ? ? 0 ? ? 01 ? rev. 1.10 119 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? motor protection function motors normally require large currents for their operation and as such need to be protected from the problems of ex cessive dr ive cu rrents, mo tor sta lling et c to re duce mo tor da mage or fo r safe ty reasons. this device includes a range of protection and safety features. mask at0 ab0 bt0 bb0 ct0 cb0 motor protect ckt opa & compare ckt is captm int0a pause fault mptc1 int0b int0c protect int_ahl_lim int_is captm_cmp captm_over mptc2 int_pau int_flt protection function block diagram pause fault flthe pswe pswd d reset opa & compare ckt captm ahlhe int_ahl_lim ishe int_is capche captm_cmp captm_over capohe protect pswps=0 pswps=1 isps=0 capcps=0 capops=0 isps=1 cacps=1 capops=1 pauhe q pauts edge ckt int_pause protection function control
rev. 1.10 118 ?a? ?0? ?01? rev. 1.10 119 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? motor protection function description this device provide s five kinds of prote ction fea tures, al lowing ac tion to be ta ken to prote ct th e motor from damage or to provide additional safety. the protection features are: 1. an external edge trigger on the pause pin - edge trigger 2. an external level trigger on fault pin - level trigger 3. stall detection function 4. over current protection 5. turn of f the motor using software when the motor protection circuit is on, the external gate drive transistor pair can be put into two different protection modes. the frst is the brake mode which is where the top arm is off and the bottom arm is on, and the second is the free running mode where both top and bottom arms are off. the fmos bit in the mcf register determines which type is used. the motor protection circuit operates in two modes, which is selected by the mptc2 register. one mode is the fault mode and the other is pause mode. in the fault mode, activating the protect function is determined by the trigger source starting status. ending the protect function is determined by the trigger source disarming status. in the pause mode, turning on the protect function is determined by the trigger source. ending the protection function is determined by software. fault pin function the fault pin is used to detect whether an external circuit has detected a motor stall or over current condition. the pin is a level trigger type and is active low and protect is "1". the fault pin and protect are controlled by fl the bit in the mptc1 register . pause pin function the pause pin is used to detect whether an external circuit has detected a motor stall or over current condition. the pause pin is edge tri ggered and prote ct is "1". it wil l ca use the ext ernal gat e driver to be shut down. the pause pin mode condition is determined by the pswd/pswe/pswps bits and prote ct is "0", the n the ext ernal gat e drive r ci rcuit is cont rolled by the hal l sensor decoder circuit. the pause pin function is controlled by the pauhe and pauts bits in the mptc1 and mptc2 registers. current protection function as the device contains a 10-bit a/d converter, an 8-bit d/a converter and an amplifer, they can be used together to measure the motor current and to detect for excessive current values. if an over current situation should occur, then the external drive circuit can be shut down immediately to prevent motor damage. the int_ahl_li mos has a current limit protection mechanism. disable the h/w mode when ahlhe is "0" and enable the h/w mode when ahlhe is "1". the limited current circuit is a hardware circuit, for which the a/d converter channel must select the operation amplifier to be active. if there is an over current during sys tem startup, then this current limit circuit should be disabled. the int_is mos has an over current protection mechanism. disable the h/w model when ishe is "0" and enable the h/w mode when ishe is "1". select the fault mode when isps is "0" and select the pause mode when isps is "1", .
rev. 1.10 1 ? 0 ? a ? ? 0 ? ? 01 ? rev. 1.10 1?1 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? pwm counter hat~hcb x6 s1 s2 s3 s4 s5 s6 15khz ~64 us gat~gcb (x6) (pwmo) time int_adc mos limited current protect (ahlhe=1;ahlps=1) start the next cycle of the pwm output automaticly by hardware int_adc pwm counter hat~hcb x6 s1 s2 s3 s4 s5 s6 15khz ~64 us gat~gcb (x6) (pwmo) time int_cmp mos over current protection (ishe=1;isps=0) restar the pwm output must by software int_cmp over current motor stall detection function for 3-phase bl dc app lications wit h hal l senso rs, th e 16-b it capt m ca n be used to mo nitor th e int0a, int0b and int0c inputs for rotor speed detection. the over current signal is selected by the captmah and captmal registers which can monitor the hall sensor input pins int0a, int0b and int0c to detect the rotor speed. when an over current condition occurs, a captm_ cmp or captm_over int errupt wil l be ge nerated. re fer to th e capt m ch apter fo r de tails. in th e captm_cmp stall detect mechanism, disable the h/w mode when capche is "0", and enable the h/w mode when capche is "1". select the fault mode when capcps is "0" and select the pause mode when capcps is "1". in the captm_over stall detect mechanism, disable the h/w mode when capohe is "0" and enable the h/w mode when capohe is "1". select the fault mode when capops is "0" and select the pause mode when capops is "1". motor protection circuit register description there are two regi sters, mptc1 and mptc2, whic h are used for the mot or prote ction cont rol function.
rev. 1.10 1?0 ?a? ?0? ?01? rev. 1.10 1 ? 1 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mptc1 register bit 7 6 5 4 3 2 1 0 name pswd pswe capohe capche ishe ahlhe pauhe flthe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pswd: protect s/w mode data 0: pswd=0 1: pswd=1 bit 6 pswe: protect s/w mode enable 0: disable 1: enable bit 5 capohe: captm_over h/w mode enable 0: disable 1: enable bit 4 capche: captm_cmp h/w mode enable 0: disable 1: enable bit 3 ishe: int_is h/w mode enable 0: disable 1: enable bit 2 ahlhe: int_ahl_lim h/w mode enable 0: disable 1: enable bit 1 pauhe: pause pin h/w mode enable 0: disable 1: enable bit 0 flthe: fault pin h/w mode enable 0: disable 1: enable
rev. 1.10 1 ?? ? a ? ? 0 ? ? 01 ? rev. 1.10 1?? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mptc2 register bit 7 6 5 4 3 2 1 0 name pauts1 pauts0 pswps ahlps isps capcps capops r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6~5 pauts1~pauts0: pause trigger select 00: disable pause int. 01: rising edge 10: falling edge 11: dual edge bit 4 pswps: pause/fault mode select 0: select fault mode 1: select pause mode bit 3 ahlps: int_ahl_lim pause/fault mode select 0: select fault mode 1: select pause mode bit 2 isps: int_is pause/fault mode select 0: select fault mode 1: select pause mode bit 1 capcps: captm_cmp pause/fault mode select 0: select fault mode 1: select pause mode bit 0 capops: captm_over pause/fault mode select 0: select fault mode 1: select pause mode
rev. 1.10 1?? ?a? ?0? ?01? rev. 1.10 1 ?? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? motor position detection methods there are three me thods of bl dc mo tor po sitioning co ntrol av ailable. th ese ar e dig ital hal l sen sor method, linear hall sensor method and sensorless method. digital hall sensor method in this method there are three external digital outputs from the hall sensors to detect the rotor position. int0a, int0b and int0c can detect rising, falling and dual edge trigger interrupts. the numerical changes from the hall sensors is detected is controlled by the application program and can be used to monitor the rotor position . here ha/hb/hc and the 12 hall decoder registers are used to control th e di rection of mo tor. th e pwm fu nctional bl ock is use d to co ntrol th e mo tor spe ed. hall detect int0[a/b/c] hb ha hc digital hall sensor method linear hall sensor method: in this method a linear hall sensor to detect the rotor position. the numerical changes of the external linear hall sensor is monitored by the 8-bit dac, 10-bit adc and comparator 1. the lhmc register, hacm, and the int_hbdet or int_ahl_lim, are used to monitor the motor position. here sha/shb/shc an d th e 12 hal l de coding re gisters ar e use d to co ntrol th e mot or di rection. th e pwm functional block is used to control the motor speed. linear hall detect hb int _hbdet int _ahl _ lim adr linear hall sensor method sensorless method in this method the 3 channels, an0/an1/an2, of the 10-bit a/d converter is used to detect the changes in the back emf of the three-phase motor. the changes can be detected by the int_ad_ eoc, int_ahl_lim and adrl/adrh registers. there is a set of 16-bit ctms to monitor the position and speed of the motor. use sha/shb/shc and the 12 hall decoder registers to control the motor direction. the pwm functional block is used to control the motor speed. e?f detect int _ad_ eoc v u w int _ahl _ lim adr sensorless method
rev. 1.10 1 ? 4 ? a ? ? 0 ? ? 01 ? rev. 1.10 1?5 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? dc motor control the device can control motors using 1 or 2 pins. taking the example of dc fan head motor control. a 2-pin dc motor interface can control the fan head motor speed and direction, while the 1-pin dc motor interface can only control the motor speed. the fh_ms bit in the dcmcr1 register is used to select either a 1-pin or 2-pin dc motor interface. 2-pin dc motor control in this case the 2-pin dc motor interface can control both the motor speed and direction. an external circuit using a limit switch or a vr circuit can be used to control the motor direction. the 10-bit ctm output pwmo is used to adjust the pwm duty cycle to control dc motor speed. the dc_mctl circuit controls the dc motor direction. vddm=5v fh0_sat fh0_sbt fh0_ri fh0_li HT45FM2C 10-bit ctm tmr0 pwmo fh0_fr fh0_stop p p n n l_lsw r_lsw vddm=5v fh1_sat fh1_sbt fh1_ri fh1_li 10-bit ctm tmr1 pwmo fh1_fr fh1_stop p p n n l_lsw r_lsw dc_mctl dc_mctl fh0_pa fh0_pb fh1_pa fh1_pb vddm=5v vddm=5v vddm=5v vddm=5v fh_ms 0 1 1 0 fh_ms 0 1 1 0 1 1 2-pin dc motor interface application circuit the dc control order for the motor direction is that the motor should be free (fh [0/1] _stop) before forward (fh [0/1] _fr) and then change direction. it is used to adjust the output polarity according to the external gate drive confguration (p type or n type). the dc fan head interface reset default value is fh0_sat = hi-z/fh0_sbt = hi-z and fh1_sat = hi-z/fh1_sbt = hi-z. fh[0/1]_stop fh[0/1]_fr dc_motor 0 1 forward 0 0 backward 1 v free
rev. 1.10 1?4 ?a? ?0? ?01? rev. 1.10 1 ? 5 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? 1-pin dc motor control the 1-pin dc motor interface is used only to control the motor speed. the 10-bit ctm output pwmo is used to adjust the pwm duty cycle to control the dc motor speed. it is used to adjust the output polarity according to the external gate drive confguration (p type or n type). the dc fan head interface reset default value is fh1_sat= hi-z /fh1_sbt=hi-z. vddm=5v p n vddm=5v p vddm=5v vddm=5v fh0_sat fh0_sbt fh0_ri fh0_li HT45FM2C 10-bit ctm tmr0 pwmo fh0_fr fh0_stop fh1_sat fh1_sbt fh1_ri fh1_li 10-bit ctm tmr1 pwmo fh1_fr fh1_stop dc_mctl dc_mctl fh0_pa fh0_pb fh1_pa fh1_pb fh_ms 0 1 1 0 fh_ms 0 1 1 0 1 1 1-pin dc motor interface application circuit
rev. 1.10 1 ? 6 ? a ? ? 0 ? ? 01 ? rev. 1.10 1?7 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? register description two registers, dcmcr0 and dcmcr1 are used for overall control. dcmcr0 register bit 7 6 5 4 3 2 1 0 name fh1_pb fh1_pa fh0_pb fh0_pa fh1_stop fh1_fr fh0_stop fh0_fr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 0 1 0 bit 7 fh1_pb: polarity output control 0: non-inverse 1: inverse bit 6 fh1_pa: polarity output control 0: non-inverse 1: inverse bit 5 fh0_pb: polarity output control 0: non-inverse 1: inverse bit 4 fh0_pa: polarity output control 0: non-inverse 1: inverse bit 3 fh1_stop: fan head 1 stop enable 0: motor normal operation 1: motor free run bit 2 fh1_fr: fan head 1 direction select 0: backward 1: forward bit 1 fh0_stop: fan head 0 stop enable 0: motor normal operation 1: motor free run bit 0 fh0_fr: fan head 0 direction select 0: backward 1: forward dcmcr1 register bit 7 6 5 4 3 2 1 0 name fh1_be fh1_ae fh0_be fh0_ae fh_ ? s r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as "0" bit 4~1 fh[1/0]_[a/b]e: fan head interface output enable 0: disable fan head interface output 1: enable fan head interface output bit 0 fh_ms: fan head mode select 0: 1-pin mode for 1 fan head 1: 2-pin mode for 1 fan head
rev. 1.10 1?6 ?a? ?0? ?01? rev. 1.10 1 ? 7 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? interrupts interrupts are an important part of any microcontroller sys tem. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. this device contains six external interrupt and 21 internal interrupt functions. the external interrupts are generated by the action of the external int0a, int0b, int0c, int1, fault and pause pins, while the internal interrupts are generated by various internal functions such as the 10-bit or 16-bit ctms, comparators, motor protect, linear hall sensor detect, pwm module, 16-bit captm module, 8-bit rmt module, time base, lvd, eeprom and the a/d converter . interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers fall into two categories. the frst is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi8 registers which setup the multi-function interrupts. each register contains a number of enable bits to enable or disabl e individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global e ? i external interrupt 0 (hall sensor) halle hallf halae halaf halbe halbf halce halcf external interrupt 1 int1e int1f comparator cne cnf n=0 ? 1 ? ultifunction interrupt ? fne ? fnf n=1~8 a/d converter aeoce aeocf ali ? e ali ? f external fault interrupt flte fltf external pause interrupt paue pauf pw ? pw ? de pw ? df pw ? pe pw ? pf time base tbe tbf capt ? capoe capof capce capcf t ? t ? nae t ? naf n=0 ? 1 ????? 5 t ? npe t ? npf n=0 ? 1 ????? 5 r ? t r ? t0e r ? t0f r ? t1e r ? t1f r ? tve r ? tvf lvd lvde lvdf eepro ? epwe epwf interrupt register bit naming conventions
rev. 1.10 1 ? 8 ? a ? ? 0 ? ? 01 ? rev. 1.10 1?9 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? interrupt register contents name bit 7 6 5 4 3 2 1 0 intc0 c0f int1f hallf c0e int1e halle e ? i intc1 pauf fltf ? f1f c1f paue flte ? f1e c1e intc ? ? f4f ? f ? f tbf ? f ? f ? f4e ? f ? e tbe ? f ? e intc ? ? f8f ? f7f ? f6f ? f5f ? f8e ? f7e ? f6e ? f5e ? fi0 halcf halbf halaf halce halbe halae ? fi1 ali ? f aeocf ali ? e aeoce ? fi ? pw ? pf pw ? df pw ? pe pw ? de ? fi ? capcf capof capce capoe ? fi4 t ? 1af t ? 1pf t ? 0af t ? 0pf t ? 1ae t ? 1pe t ? 0ae t ? 0pe ? fi5 t ?? af t ?? pf t ?? af t ?? pf t ?? ae t ?? pe t ?? ae t ?? pe ? fi6 r ? tvf r ? t1f r ? t0f r ? tve r ? t1e r ? t0e ? fi7 t ? 5af t ? 5pf t ? 5ae t ? 5pe ? fi8 epwf lvdf epwe lvde intc0 register bit 7 6 5 4 3 2 1 0 name c0f int1f hallf c0e int1e halle e ? i r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 cp0f: comparator 0 interrupt request fag 0: no request 1: interrupt request bit 5 int1f: external 1 interrupt request fag 0: no request 1: interrupt request bit 4 hallf: hall sensor global interrupt request fag 0: no request 1: interrupt request bit 3 c0e: comparator 0 interrupt control 0: disable 1: enable bit 2 int1e: external 1 interrupt control 0: disable 1: enable bit 1 halle: hall sensor global interrupt control 0: disable 1: enable bit 0 emi: global interrupt control 0: disable 1: enable
rev. 1.10 1?8 ?a? ?0? ?01? rev. 1.10 1 ? 9 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? intc1 register bit 7 6 5 4 3 2 1 0 name pauf fltf ? f1f c1f paue flte ? f1e c1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pauf: pause interrupt request flag 0: no request 1: interrupt request bit 6 fltf: fault interrupt request flag 0: no request 1: interrupt request bit 5 mf1f: multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 4 c1f: comparator 1 interrupt request flag 0: no request 1: interrupt request bit 3 paue: pause interrupt interrupt control 0: disable 1: enable bit 2 flte: fault interrupt control 0: disable 1: enable bit 1 mf1e: multi-function interrupt 1 control 0: disable 1: enable bit 0 c1e: comparator 1 interrupt control 0: disable 1: enable
rev. 1.10 1 ? 0 ? a ? ? 0 ? ? 01 ? rev. 1.10 1?1 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ?
rev. 1.10 1?0 ?a? ?0? ?01? rev. 1.10 1 ? 1 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? intc2 register bit 7 6 5 4 3 2 1 0 name ? f4f ? f ? f tbf ? f ? f ? f4e ? f ? e tbe ? f ? e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf4f: multi-function interrupt 4 request fag 0: no request 1: interrupt request bit 6 mf3f: multi-function interrupt 3 request fag 0: no request 1: interrupt request bit 5 tbf: time base interrupt request fag 0: no request 1: interrupt request bit 4 mf2f: multi-function interrupt 2 request fag 0: no request 1: interrupt request bit 3 mf4e: multi-function interrupt 4 control 0: disable 1: enable bit 2 mf3e: multi-function interrupt 3 control 0: disable 1: enable bit 1 tbe: time base interrupt control 0: disable 1: enable bit 0 mf2e: multi-function interrupt 2 control 0: disable 1: enable
rev. 1.10 1 ?? ? a ? ? 0 ? ? 01 ? rev. 1.10 1?? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? intc3 register bit 7 6 5 4 3 2 1 0 name ? f8f ? f7f ? f6f ? f5f ? f8e ? f7e ? f6e ? f5e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf8f: multi-function interrupt 8 request fag 0: no request 1: interrupt request bit 6 mf7f: multi-function interrupt 7 request fag 0: no request 1: interrupt request bit 5 mf6f: multi-function interrupt 6 request fag 0: no request 1: interrupt request bit 4 mf5f: multi-function interrupt 5 request fag 0: no request 1: interrupt request bit 3 mf8e: multi-function interrupt 8 control 0: disable 1: enable bit 2 mf7e: multi-function interrupt 7 control 0: disable 1: enable bit 1 mf6e: multi-function interrupt 6 control 0: disable 1: enable bit 0 mf5e: multi-function interrupt 5 control 0: disable 1: enable
rev. 1.10 1?? ?a? ?0? ?01? rev. 1.10 1 ?? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mfi0 register bit 7 6 5 4 3 2 1 0 name halcf halbf halaf halce halbe halae r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 halcf: hall sensor c interrupt request fag 0: no request 1: interrupt request bit 5 halbf: hall sensor b interrupt request fag 0: no request 1: interrupt request bit 4 halaf: hall sensor a interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as "0" bit 2 halce: hall sensor c interrupt control 0: disable 1: enable bit 1 halbe: hall sensor b interrupt control 0: disable 1: enable bit 0 halae: hall sensor a interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 name ali ? f aeocf ali ? e aeoce r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 alimf: a/d converter eoc compare interrupt request fag 0: no request 1: interrupt request bit 4 aeocf: a/d converter interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 alime: a/d converter eoc compare interrupt control 0: disable 1: enable bit 0 aeoce: a/d converter interrupt control 0: disable 1: enable
rev. 1.10 1 ? 4 ? a ? ? 0 ? ? 01 ? rev. 1.10 1?5 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mfi2 register bit 7 6 5 4 3 2 1 0 name pw ? pf pw ? df pw ? pe pw ? de r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 pwmpf: pwm period match interrupt request fag 0: no request 1: interrupt request bit 4 pwmdf: pwm duty match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 pwmpe: pwm period match interrupt control 0: disable 1: enable bit 0 pwmde: pwm duty match interrupt control 0: disable 1: enable mfi3 register bit 7 6 5 4 3 2 1 0 name capcf capof capce capoe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 capcf: captm compare match interrupt request fag 0: no request 1: interrupt request bit 4 capof: captm capture overfow interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 capce: captm compare match interrupt control 0: disable 1: enable bit 0 capoe: captm capture overfow interrupt control 0: disable 1: enable
rev. 1.10 1?4 ?a? ?0? ?01? rev. 1.10 1 ? 5 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mfi4 register bit 7 6 5 4 3 2 1 0 name t ? 1af t ? 1pf t ? 0af t ? 0pf t ? 1ae t ? 1pe t ? 0ae t ? 0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tm1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 tm1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 tm0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 tm0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 tm1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 2 tm1pe : tm1 comparator p match interrupt control 0: disable 1: enable bit 1 tm0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 tm0pe : tm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.10 1 ? 6 ? a ? ? 0 ? ? 01 ? rev. 1.10 1?7 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mfi5 register bit 7 6 5 4 3 2 1 0 name t ?? af t ?? pf t ?? af t ?? pf t ?? ae t ?? pe t ?? ae t ?? pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tm3af : tm3 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 tm3pf : tm3 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 tm2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 tm2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 tm3ae : tm3 comparator a match interrupt control 0: disable 1: enable bit 2 tm3pe : tm3 comparator p match interrupt control 0: disable 1: enable bit 1 tm2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 0 tm2pe : tm2 comparator p match interrupt control 0: disable 1: enable
rev. 1.10 1?6 ?a? ?0? ?01? rev. 1.10 1 ? 7 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mfi6 register bit 7 6 5 4 3 2 1 0 name r ? tvf r ? t1f r ? t0f r ? tve r ? t1e r ? t0e r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 rmtvf : rmt overfow interrupt request fag 0: no request 1: interrupt request bit 5 rmt1f : rmt falling edge interrupt request fag 0: no request 1: interrupt request bit 4 rmt0f : rmt rasing edge interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as "0" bit 2 rmtve : rmt overfow interrupt control 0: disable 1: enable bit 1 rmt1e : rmt falling edge interrupt control 0: disable 1: enable bit 0 rmt0e : rmt rasing edge interrupt control 0: disable 1: enable mfi7 register bit 7 6 5 4 3 2 1 0 name t ? 5af t ? 5pf t ? 5ae t ? 5pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 tm5af : tm5 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 tm5pf : tm5 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 tm5ae : tm5 comparator a match interrupt control 0: disable 1: enable bit 0 tm5pe : tm5 comparator p match interrupt control 0: disable 1: enable
rev. 1.10 1 ? 8 ? a ? ? 0 ? ? 01 ? rev. 1.10 1?9 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mfi8 register bit 7 6 5 4 3 2 1 0 name epwf lvdf epwe lvde r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 epwf: data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvdf: lvd interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 epwe: data eeprom interrupt control 0: disable 1: enable bit 0 lvde: lvd interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur, such as a tm compare p or compare a match or a/d conversion completion etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt i s gene rated, t he program counte r, whi ch st ores the a ddress of t he next i nstruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying dia grams wit h the ir order of priori ty. some int errupt source s have the ir own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is ser viced, al l th e ot her in terrupts wil l be bl ocked, as th e gl obal in terrupt en able bi t, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from
rev. 1.10 1?8 ?a? ?0? ?01? rev. 1.10 1 ? 9 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of th e in terrupt re quest fags whe n set wil l wak e-up the de vice if it is in sle ep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. ?ulti-function 0 int1 hallf int1f halle int1e e?i 04h e?i 08h c?p0 c0f c0e e?i 0ch 10h c?p1 c1f c1e e?i 14h ?ulti-function 1 ?f1f ?f1e e?i 18h fault fltf flte e?i interrupt name request flags enable bits ?aster enable vector e?i auto disabled in isr low int0b halbf halbe int0c halcf halce int0a halaf halae interrupts contained within ? ulti- function interrupts priorit? high xxe enable bits xxf request flag ? auto reset in isr legend xxf request flag ? no auto reset in isr 1c h ?0h ?4h ?8h ?ch ?0h ?4h ?8h ?ch ?f?f ?f?e e?i pause pauf paue e?i ?f8f ?f8e e?i ?f7f ?f7e e?i ?f6f ?f6e e?i ?f5f ?f5e e?i ?f4f ?f4e e?i ?f?f ?f?e e?i time base tbf tbe e?i ?ulti-function ? ?ulti-function ? ?ulti-function 4 ?ulti-function 5 ?ulti-function 6 ?ulti-function 7 ?ulti-function 8 ahl_lim ali?f ali?e aeocf aeoce pw?p pw?pf pw?pe pw?d pw?df pw?de capcf capce capt?_over capof capoe t?0 a t?0af t?0ae t?0 p t?0pf t?0pe t?1 a t?1af t?1ae t?1 p t?1pf t?1pe adc eoc capt?_cmp t?? a t??af t??ae t?? p t??pf t??pe t?? a t??af t??ae t?? p t??pf t??pe r?t 1 r?t1f r?t1e r?t 0 r?t0f r?t0e r?t v r?tvf r?tve t?5 a t?5af t?5ae t?5 p t?5pf t?5pe eepro? epwf epwe lvd lvdf lvde interrupt structure
rev. 1.10 140 ? a ? ? 0 ? ? 01 ? rev. 1.10 141 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? external interrupt 0 the external in terrupt 0 , also known as th e hall sensor interrupt, is co ntained wit hin th e mul ti- function interrupt. it is controlled by signal transitions on the pins, hall sensor input pins, int0a, int0b and int0c. an external interrupt request will take place when the external interrupt request flag, halaf halb f an d halc f is set , whi ch wil l oc cur whe n a tr ansition, ap pears on th e external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the multi-function interrupt controlled bit, halle must frst be set. when the mult i-function int errupt cont rolled bit hall e is ena bled and the stac k is not full , and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts and the related multi-function request flag ha llf, will be automatically reset, but the multi-function interrupt request flags, halaf,halbf,halcf, must be manually cleared by the application program.. external interrupt 1 the external int errupt 1 is cont rolled by signa l tra nsitions on the pin int1. an ext ernal int errupt request will take place when the external interrupt request flag, int1f, is set, which will occurs when a transition appears on the external interrupt pin. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int1e, must frst be set. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fag, int1f, will be au tomatically re set an d th e emi bi t wil l be au tomatically cl eared to di s able other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. comparator interrupt the comparator interrupts are controlled by the two internal comparators. a comparator interrupt request will take plac e when the compara tor int errupt request fag, c0f or c1f, is set, a situa tion that will occur when the com parator output cha nges sta te. to al low the program to branc h to it s respective interrupt vec tor add ress, th e glob al in terrupt en able bit , emi, and co mparator in terrupt enable bit, c0e or c1e, must frst be set. when the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, wil l ta ke pla ce. whe n the int errupt is servi ced, the com parator int errupt req uest flags, c0f or c1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt within this device are nine multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the hall sensor interrupts, a/d interrupts, pwm module interrupts, captm interrupts, tm interrupts, rmt interrupts, eeprom and l vd interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, hallf and mf1f~mf8f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. to allow the program to branch to its respective interrupt vec tor ad dress, whe n the mul ti-function int errupt is ena bled and the sta ck is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a
rev. 1.10 140 ?a? ?0? ?01? rev. 1.10 141 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that , alt hough the mult i-function interrupt fags wil l be aut omatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the hall sensor interrupts, a/d interrupts, pwm module interrupts, captm interrupts, tm interrupts, rmt interrupt s, eeprom and lvd interrupt will not be automatica lly reset and must be manually reset by the application program. a/d converter interrupt the a/d converter has two in terrupts. all of th em are con tained in mult i-function in terrupt. the one is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, alimf, is set, which occurs when the a/d conversion process fnishes. the other is controlled by the adchve/adclve bit in the adcr1 registe r and the value in the adlvdh/ adlvdl and adhvdh/adhvdl boundary control registers. an a/d converter interrupt request will take place after eoc comparing. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, aeoce or alime, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended or after eoc comparing a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d converter interrupt fag, aeocf or alimf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. fault interrupt fault pin is motor control disable pin, it supports low active level trigger interrupt. when this happens, its interrupt request fag, fltf will be set. to allow the program to branch to its interrupt vector address, the global interrupt enable bit, emi and enable bit, flte, must frst be set. when the interrupt is enabled, the stack is not full and a low active level appears on the pin, a subroutine call to this vector location will take place. when the interrupt is serviced, the interrupt request fag, fltf, will be automatically reset and the emi bit will be cleared to disable other interrupts. pause interrupt pause pin is motor control enable pin, it support rising/fal ling/both tri gger interrupt . when thi s happens, its interrupt request fag, pauf will be set. to allow the program to branch to its interrupt vector address, the global interrupt enable bit, emi and the corresponding enable bit, paue, must frst be set. when the interrupt is enabled, the stack is not full and a rising/falling/both edge trigger appears on the pin, a subroutine call to this vector location will take place. when the interrupt is serviced, the interrupt request fag, pauf, will be automatically reset and the emi bit will be cleared to disable other interrupts. pwm module interrupts the pwm module has two int errups. the two of the m are cont ained in mul ti-function int errupt, which is known as pwmd and pwmp. they are the duty or the period maching of the pwm module. an pwm interrupt request will take place when the pwm interrupt request fag, pwmdf or pwmpf, is set, which occurs when the pwm duty or pwm period matches. when the interrupt is enabled, th e sta ck is no t fu ll an d pwm dut y or pwm per iod ma ches, a sub routine ca ll to th is vector location will take place. when the interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts and the related multi-function request fag will be automatically
rev. 1.10 14 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 14? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? reset, but the interrupt request flag, pwmdf or pwmpf, must be manually cleared by the application program. time base interrupt the function of the time base interrupt is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from its timer function. when this happens its interrupt request fag, tbf will be set. to allow the program to branch to its interrupt vector address, the global interrupt enable bit, emi and time base enable bit, tbe, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfow, a subroutine call to its vector location will take place. when the interrupt is serviced, the interrupt request fag, tbf, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. its clock source originates from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section. tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb1 tb0 r/w r/w r/w r/w r/w por 0 0 1 1 bit 7 tbon: tb control 0: disable 1: enable bit 6 tbck: select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb1~tb0: select time base time-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3~0 unimplemented, read as "0"

time base interrupt
rev. 1.10 14? ?a? ?0? ?01? rev. 1.10 14 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? captm module interrupt the captm module has two interrupts. all of them are contained within the multi-function interrupt, whi ch ar e kn own as ca ptm_over an d ca ptm_cmp. a capt m in terrupt re quest wil l take place when the captm interrupts request fag, capof or capcf, is set, which occurs when captm capture overfows or compare maches. to allow the program to branch to their respective interrupt vector address, the global interrupt enable bit, emi, and the captm interrupt enable bit, and muti-function int errupt ena ble bit , must frst be set . whe n the int errupt is ena bled, the sta ck is not full and cap tm capture overfow s or compare maches, a subroutine call to the respective multi-function interrupt vector , will take place. when the captm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the capof and capcf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupt the compact tm has two interrupts. all of the tm interrupts are contained within the multi- function interrupts. for the compact type tm, there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request fags is set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. rmt module interrupt the rmt module has three interrupts. all of them are contained within the multi-function interrupt, which are known as rmt0, rmt1 and rmtv. the rmt interrupts request will take place when the rmt interrupts request fag, rmt0f, rmt1f or rmtvf, is set, which will occurs when raising edge transition or falling edge transition appears on the rx_in pin or timer overfows. to allow the program to branch to their respective interrupt vector address, the global interrupt enable bit, emi, rmt interrupt enable bit, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and raising edge transition or falling edge transition appears on the rx_in pin or timer overflow, a subroutine call to the respective multi-function interrupt, will take place. when the rmt interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the rmt0, rmt1 and rmtv fags will not be automatically cleared, thy have to be cleared by the application program. eeprom interrupt the eeprom interrupt, is contained within the multi-function interrupt. an eepro m interrupt request will take place when the eeprom interrupt request fag, epwf, is set, which occurs when an eeprom write or read cycle ends. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, eeprom interrupt enable bit, epwe, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom write cycle ends, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be
rev. 1.10 144 ? a ? ? 0 ? ? 01 ? rev. 1.10 145 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the epwf fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the low voltage det ector int errupt is co ntained wit hin th e mul ti-function int errupt. an lvd interrupt request will take place when the lv d interrupt request fag, lv df, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lvde, and associated multi-function interrupt enable bit, must first be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit wil l be aut omatically cl eared to disa ble oth er int errupts, howe ver onl y the multi-function interrupt request fag will be also automatically cleared. as the lvdf fag will not be automatically cleared, it has to be cleared by the application program. interrupt wake-up function each of the interrupt functions has the capa bility of waking up the microc ontroller when in the sleep or idle mod e. a wak e-up is ge nerated whe n an in terrupt re quest fag ch anges fr om lo w to high and is independent of whether the interrupt is enabled or not. therefore, even though this device are in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respecti ve interrupt flag to be set high and consequently generate an interrupt. ca re mu st th erefore be ta ken if spu rious wak e-up sit uations ar e to be av oided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling th e rel evant int errupt ena ble bit s, a reque sted int errupt ca n be preve nted from bei ng serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is ex ecuted, as on ly th e mul ti-function in terrupt re quest fl ags, hall f an d mf1f~mf8f, will be automatically cleared, the individual request fag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in the sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their cont ents should be save d to the me mory at the begi nning of the int errupt servi ce
rev. 1.10 144 ?a? ?0? ?01? rev. 1.10 145 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. low voltage detector C lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low v oltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vl vd0, are used to select one of eight fxed voltages below which a low voltage con dition wil l be det ermined. a low vol tage con dition is ind icated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 lvdo: lvd output flag 0: no low voltage detect 1: low voltage detect bit 4 lvden: low voltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 vlvd2~vlvd0: select lvd voltage 000: 3.6v 001: 3.6v 010: 3.6v 011: 3.6v 100: 3.0v 101: 3.6v 110: 3.6v 111: 3.6v
rev. 1.10 146 ? a ? ? 0 ? ? 01 ? rev. 1.10 147 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a specifed voltage 3.6v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvd en bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low voltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvdf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvdf fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.10 146 ?a? ?0? ?01? rev. 1.10 147 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? application circuits hall sensor 3 h1 h? h? vdd pb?/rxin/int1/tp?_0 vss pc7/pause/tp5_1 pa0/an0/int0a pa1/an1/int0b pa?/an?/int0c pb0 pb?/is pc6/fault/tp5_0 pc5/gcb pc4/gct pc?/gbb pc?/gbt pc1/gab pc0/gat vdd hin lin co? vb ho vs lo vdd hin lin co? vb ho vs lo vdd hin lin co? vb ho vs lo ip-n ip-l drain drain drain drain vdd fb source source dc+?70v +15v +5v viper1? ir?101 ir?101 ir?101 ir rx ckt vin gnd vout dc +5v ht7150 dc+?70v dc+?70v ac??0v dc +15v ht45f??c v v dc+?70v pb7/tck0 pb6/tp0_0 pb5/tp1_0 pb4/tck? ke? ?atix ?x? pa?/an?/tck5 pb1/tp?_1 buzzer v gate driver ckt pd0/fh1_sat/tp0_1 pd1/fh1_sbt/tp1_1 pa4/an4/fh0_sat/tck? pa5/an5/fh0_sbt/tp?_1 pa7/an7/fh0_ri/tck1 pa6/an6/fh0_li/tp?_0 pd?/fh1_li pd?/fh1_ri v gate driver ckt pull-low or pull-high
rev. 1.10 148 ? a ? ? 0 ? ? 01 ? rev. 1.10 149 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? hall sensor 1 h? vdd vss pc7/pause/tp5_1 pa0/an0/int0a pa1/an1/int0b pa?/an?/int0c pb0 pb?/is pc6/fault/tp5_0 pc5/gcb pc4/gct pc?/gbb pc?/gbt pc1/gab pc0/gat vdd hin lin co? vb ho vs lo vdd hin lin co? vb ho vs lo vdd hin lin co? vb ho vs lo ip-n ip-l drain drain drain drain vdd fb source source dc+?70v +15v +5v viper1? ir?101 ir?101 ir?101 ir rx ckt vin gnd vout dc +5v ht7150 dc+?70v dc+?70v ac??0v dc +15v ht45f??c v v dc+?70v +5v pb7/tck0 pb6/tp0_0 pb5/tp1_0 pb4/tck? ke? ?atix ?x? pa?/an?/tck5 pb1/tp?_1 buzzer v gate driver ckt pd0/fh1_sat/tp0_1 pd1/fh1_sbt/tp1_1 pa4/an4/fh0_sat/tck? pa5/an5/fh0_sbt/tp?_1 pa7/an7/fh0_ri/tck1 pa6/an6/fh0_li/tp?_0 pd?/fh1_li pd?/fh1_ri v gate driver ckt pull-low or pull-high pb?/rxin/int1/tp?_0
rev. 1.10 148 ?a? ?0? ?01? rev. 1.10 149 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? non-hall sensor vdd vss pb1/tp?_1 pc7/pause/tp5_1 pa0/an0/int0a pa1/an1/int0b pa?/an?/int0c pb0 pb?/is pc6/fault/tp5_0 pc5/gcb pc4/gct pc?/gbb pc?/gbt pc1/gab pc0/gat vdd hin lin co? vb ho vs lo vdd hin lin co? vb ho vs lo vdd hin lin co? vb ho vs lo ip-n ip-l drain drain drain drain vdd fb source source dc+?70v +15v +5v viper1? ir?101 ir?101 ir?101 ir rx ckt vi n gn d vou t dc +5v ht7150 dc+?70v dc+?70v ac??0v dc +15v ht45f??c buzzer v v v gate driver ckt back e?f & filter ckt dc+?70v pb7/tck0 pb6/tp0_0 pb5/tp1_0 pb4/tck? ke? ?atix ?x? pa?/an?/tck5 pd0/fh1_sat/tp0_1 pd1/fh1_sbt/tp1_1 pa4/an4/fh0_sat/tck? pa5/an5/fh0_sbt/tp?_1 pa7/an7/fh0_ri/tck1 pa6/an6/fh0_li/tp?_0 pd?/fh1_li pd?/fh1_ri v gate driver ckt pull-low pull-high pb?/rxin/int1/tp?_0
rev. 1.10 150 ? a ? ? 0 ? ? 01 ? rev. 1.10 151 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented wit hin 0.5s and branc h or ca ll inst ructions would be im plemented wit hin 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to tha t new addre ss, one more cyc le wil l be requi red. exa mples of such inst ructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of dat a wit hin the mi crocontroller program is one of the most freque ntly used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most im portant dat a tra nsfer appl ications is to rec eive dat a from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller appl ications. wi thin the holt ek mi crocontroller inst ruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.10 150 ?a? ?0? ?01? rev. 1.10 151 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within the holt ek mi crocontroller inst ruction set. as wit h the ca se of most inst ructions invol ving data manipulation, da ta mu st pa ss th rough th e acc umulator whi ch ma y in volve ad ditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming app lications where dat a ca n be rota ted from an int ernal regi ster int o the carry bit from where it can be examined and the necessary serial bit set high or low. another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call inst ruction. the y dif fer in the sense tha t in the ca se of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. thi s is done by pla cing a ret urn inst ruction re t in the subrouti ne which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a ce rtain dat a me mory or indi vidual bit s. depe nding upon the condi tions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to dec ision ma king and branc hing wit hin the program perha ps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is norma lly im plemented by using regi sters. however, when working wit h la rge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.10 15 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 15? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] add data ? emor ? to acc 1 z ? c ? ac ? ov add ? a ? [m] add acc to data ? emor ? 1 note z ? c ? ac ? ov add a ? x add immediate data to acc 1 z ? c ? ac ? ov adc a ? [m] add data ? emor ? to acc with carr ? 1 z ? c ? ac ? ov adc ? a ? [m] add acc to data memor ? with carr ? 1 note z ? c ? ac ? ov sub a ? x subtract immediate data from the acc 1 z ? c ? ac ? ov sub a ? [m] subtract data ? emor ? from acc 1 z ? c ? ac ? ov sub ? a ? [m] subtract data ? emor ? from acc with result in data ? emor ? 1 note z ? c ? ac ? ov sbc a ? [m] subtract data ? emor ? from acc with carr ? 1 z ? c ? ac ? ov sbc ? a ? [m] subtract data ? emor ? from acc with carr ?? result in data ? emor ? 1 note z ? c ? ac ? ov daa [m] decimal adjust acc for addition with result in data ? emor ? 1 note c logic operation and a ? [m] logical and data ? emor ? to acc 1 z or a ? [m] logical or data ? emor ? to acc 1 z xor a ? [m] logical xor data ? emor ? to acc 1 z and ? a ? [m] logical and acc to data ? emor ? 1 note z or ? a ? [m] logical or acc to data ? emor ? 1 note z xor ? a ? [m] logical xor acc to data ? emor ? 1 note z and a ? x logical and immediate data to acc 1 z or a ? x logical or immediate data to acc 1 z xor a ? x logical xor immediate data to acc 1 z cpl [m] complement data ? emor ? 1 note z cpla [m] complement data ? emor ? with result in acc 1 z increment & decrement inca [m] increment data ? emor ? with result in acc 1 z inc [m] increment data ? emor ? 1 note z deca [m] decrement data ? emor ? with result in acc 1 z dec [m] decrement data ? emor ? 1 note z rotate rra [m] rotate data ? emor ? right with result in acc 1 none rr [m] rotate data ? emor ? right 1 note none rrca [m] rotate data ? emor ? right through carr ? with result in acc 1 c rrc [m] rotate data ? emor ? right through carr ? 1 note c rla [m] rotate data ? emor ? left with result in acc 1 none rl [m] rotate data ? emor ? left 1 note none rlca [m] rotate data ? emor ? left through carr ? with result in acc 1 c rlc [m] rotate data ? emor ? left through carr ? 1 note c
rev. 1.10 15? ?a? ?0? ?01? rev. 1.10 15 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? mnemonic description cycles flag affected data move ? ov a ? [m] ? ove data ? emor ? to acc 1 none ? ov [m] ? a ? ove acc to data ? emor ? 1 note none ? ov a ? x ? ove immediate data to acc 1 none bit operation clr [m].i clear bit of data ? emor ? 1 note none set [m].i set bit of data ? emor ? 1 note none branch j ? p addr jump unconditionall ? ? none sz [m] skip if data ? emor ? is zero 1 note none sza [m] skip if data ? emor ? is zero with data movement to acc 1 note none sz [m].i skip if bit i of data ? emor ? is zero 1 note none snz [m].i skip if bit i of data ? emor ? is not zero 1 note none siz [m] skip if increment data ? emor ? is zero 1 note none sdz [m] skip if decrement data ? emor ? is zero 1 note none siza [m] skip if increment data ? emor ? is zero with result in acc 1 note none sdza [m] skip if decrement data ? emor ? is zero with result in acc 1 note none call addr subroutine call ? none ret return from subroutine ? none ret a ? x return from subroutine and load immediate data to acc ? none reti return from interrupt ? none table read tabrdc [m] read table to tblh and data ? emor ? ? note none tabrdl [m] read table (last page) to tblh and data ? emor ? ? note none miscellaneous nop no operation 1 none clr [m] clear data ? emor ? 1 note none set [m] set data ? emor ? 1 note none clr wdt clear watchdog timer 1 to ? pdf clr wdt1 pre-clear watchdog timer 1 to ? pdf clr wdt ? pre-clear watchdog timer 1 to ? pdf swap [m] swap nibbles of data ? emor ? 1 note none swapa [m] swap nibbles of data ? emor ? with result in acc 1 none halt enter power down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution sta tus. the to and pdf fla gs are cl eared aft er both c lr wdt 1 and c lr wdt 2 instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.10 154 ? a ? ? 0 ? ? 01 ? rev. 1.10 155 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? instruction defnition adc a,[m] add da ta me mory to ac c wit h c arry description the co ntents of th e sp ecifed da ta me mory, ac cumulator an d th e ca rry fag ar e ad ded. the res ult i s st ored in th e ac cumulator. operation acc ac c + [m ] + c affected fag(s) ov, z, ac , c adcm a,[m] add ac c to da ta me mory wit h c arry description the co ntents of th e sp ecifed da ta me mory, ac cumulator an d th e ca rry fag ar e ad ded. the res ult i s st ored in th e spe cifed da ta me mory. operation [m] ac c + [m] + c affected fag(s) ov, z, ac , c add a,[m] add da ta memor y to ac c description the co ntents of th e sp ecifed da ta me mory an d th e ac cumulator ar e ad ded. the res ult i s st ored in th e ac cumulator. operation acc ac c + [m ] affected fag(s) ov, z, ac , c add a,x add immediate d ata to ac c description the co ntents of th e ac cumulator an d th e sp ecifed imm ediate da ta ar e ad ded. the res ult i s st ored in th e ac cumulator. operation acc ac c + x affected fag(s) ov, z, ac , c addm a,[m] add ac c to da ta me mory description the co ntents of th e sp ecifed da ta me mory an d th e ac cumulator ar e ad ded. the res ult i s st ored in th e spe cifed da ta me mory. operation [m] ac c + [m] affected fag(s) ov, z, ac , c and a,[m] logical an d da ta memor y to ac c description data in th e ac cumulator an d th e sp ecifed da ta me mory pe rform a bit wise lo gical an d operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c an d [m ] affected fag(s) z and a,x logical and imm ediate d ata to ac c description data in th e ac cumulator an d th e sp ecifed imm ediate da ta pe rform a bit wi se lo gical an d operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c an d x affected fag(s) z andm a,[m] logical an d ac c to da ta me mory description data in th e sp ecifed da ta me mory an d th e ac cumulator pe rform a bit wise lo gical an d operation. th e res ult i s st ored in th e da ta me mory. operation [m] ac c a nd [m] affected fag(s) z
rev. 1.10 154 ?a? ?0? ?01? rev. 1.10 155 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? call addr subroutine ca ll description unconditionally cal ls a su broutine at th e sp ecifed ad dress. the pr ogram cou nter th en increments by 1 to ob tain th e ad dress of th e ne xt in struction wh ich is th en pu shed on to th e stack. th e spe cifed add ress i s th en l oaded an d th e pro gram co ntinues ex ecution fro m th is new add ress. as th is in struction req uires an add itional ope ration, i t i s a tw o cy cle in struction. operation stack pr ogram c ounter + 1 program cou nter ad dr affected fag(s) none clr [m] clear da ta memor y description each bi t of th e sp ecifed da ta me mory is clea red to 0. operation [m] 0 0h affected fag(s) none clr [m].i clear bit of da ta me mory description bit i of th e sp ecifed da ta me mory is clea red to 0. operation [m].i 0 affected fag(s) none clr wdt clear wa tchdog ti mer description the to , pd f fag s an d th e wd t ar e all cl eared. operation wdt clea red to 0 pdf 0 affected fag(s) to, pd f clr wdt1 pre-clear wa tchdog ti mer description the to , pd f fa gs an d th e wd t are al l cl eared. no te th at th is in struction wo rks in conjunction wit h cl r wd t2 an d mu st be ex ecuted alt ernately wit h cl r wd t2 to ha ve effect. re petitively ex ecuting th is in struction wit hout alt ernately ex ecuting cl r wd t2 wi ll have no ef fect. operation wdt clea red to 0 pdf 0 affected fag(s) to, pd f clr wdt2 pre-clear wa tchdog ti mer description the to , pd f fa gs a nd th e wd t a re al l c leared. no te th at thi s in struction wo rks in c onjunction with cl r wd t1 an d mu st be ex ecuted alt ernately wit h cl r wd t1 to ha ve ef fect. re petitively ex ecuting th is in struction wit hout alt ernately ex ecuting cl r wd t1 wi ll ha ve no e f fect. operation wdt clea red to 0 pdf 0 affected fag(s) to, pd f cpl [m] complement da ta memor y description each bi t o f th e sp ecifed da ta me mory is lo gically c omplemented (1 s c omplement). bi ts whi ch previously co ntained a 1 ar e ch anged to 0 an d vi ce ve rsa. operation [m] [m] affected fag(s) z
rev. 1.10 156 ? a ? ? 0 ? ? 01 ? rev. 1.10 157 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? cpla [m] complement da ta me mory wit h re sult in ac c description each bi t o f th e sp ecifed da ta me mory is lo gically c omplemented (1 s c omplement). bi ts whi ch previously co ntained a 1 ar e ch anged to 0 an d vi ce ve rsa. the co mplemented re sult is sto red in the ac cumulator an d th e co ntents of th e da ta me mory re main un changed. operation acc [m] affected fag(s) z daa [m] decimal-adjust ac c fo r ad dition wit h re sult in da ta me mory description convert th e co ntents of th e ac cumulator val ue to a bc d (b inary co ded de cimal) val ue resulting fro m th e pre vious add ition of tw o bc d va riables. if th e l ow ni bble i s g reater th an 9 or if ac fag is se t, th en a val ue of 6 wi ll be ad ded to th e lo w ni bble. ot herwise th e lo w ni bble remains un changed. if th e hi gh ni bble is gr eater th an 9 or if th e c fag is se t, th en a val ue of 6 will be ad ded to th e hi gh ni bble. es sentially, th e de cimal co nversion is pe rformed by ad ding 00h, 06 h, 60 h or 66 h de pending on th e ac cumulator an d fag co nditions. on ly th e c fag may be af fected by th is in struction wh ich in dicates th at i f th e or iginal bc d su m i s g reater th an 100, it all ows mul tiple pr ecision de cimal ad dition. operation [m] ac c + 0 0h o r [m] ac c + 06h or [m] ac c + 6 0h or [m] ac c + 6 6h affected fag(s) c dec [m] decrement da ta memor y description data in th e sp ecifed da ta me mory is dec remented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement da ta memor y wit h re sult in ac c description data in th e spe cifed da ta me mory i s de cremented by 1. th e res ult i s st ored in th e accumulator. the co ntents of th e da ta me mory re main un changed. operation acc [m ] ? 1 affected fag(s) z halt enter po wer d own mo de description this in struction sto ps th e pr ogram ex ecution an d tu rns of f th e sy stem cl ock. the co ntents of the da ta me mory an d re gisters ar e re tained. the wd t an d pr escaler ar e cl eared. the po wer down fag pd f is se t an d th e wd t tim e-out fag to is cl eared. operation to 0 pdf 1 affected fag(s) to, pd f inc [m] increment da ta memor y description data in th e spe cifed da ta me mory i s in cremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memor y wit h re sult in ac c description data in th e spe cifed da ta me mory is in cremented by 1. the res ult is sto red in th e ac cumulator. the co ntents of th e da ta me mory re main un changed. operation acc [m ] + 1 affected fag(s) z
rev. 1.10 156 ?a? ?0? ?01? rev. 1.10 157 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? jmp addr jump unconditionally description the co ntents of th e pro gram co unter are rep laced wi th th e spe cifed add ress. pro gram execution th en co ntinues fro m th is ne w add ress. as th is req uires th e in sertion of a du mmy instruction wh ile th e ne w add ress i s l oaded, i t i s a tw o cy cle in struction. operation program c ounter ad dr affected fag(s) none mov a,[m] move da ta memor y to ac c description the co ntents of th e sp ecifed da ta me mory ar e co pied to th e ac cumulator. operation acc [m ] affected fag(s) none mov a,x move immediate d ata to ac c description the imm ediate da ta sp ecifed is lo aded in to th e ac cumulator. operation acc x affected fag(s) none mov [m],a move ac c to da ta me mory description the co ntents of th e ac cumulator ar e co pied to th e sp ecifed da ta me mory. operation [m] ac c affected fag(s) none nop no op eration description no op eration is pe rformed. ex ecution con tinues wi th th e ne xt in struction. operation no o peration affected fag(s) none or a,[m] logical or da ta me mory to ac c description data in th e ac cumulator an d th e sp ecifed da ta me mory pe rform a bit wise logical or ope ration. th e res ult i s st ored in th e ac cumulator. operation acc ac c o r [m ] affected fag(s) z or a,x logical o r imm ediate d ata to ac c description data in th e ac cumulator an d th e sp ecifed imm ediate da ta pe rform a bit wise lo gical or operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c o r x affected fag(s) z orm a,[m] logical o r ac c to da ta me mory description data in th e sp ecifed da ta me mory an d th e ac cumulator pe rform a bit wise lo gical or operation. th e res ult i s st ored in th e da ta me mory. operation [m] ac c o r [m] affected fag(s) z ret return f rom su broutine description the pro gram co unter i s res tored fro m th e st ack. pro gram ex ecution co ntinues at th e res tored a dd ress. operation program c ounter st ack affected fag(s) none
rev. 1.10 158 ? a ? ? 0 ? ? 01 ? rev. 1.10 159 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? ret a,x return fr om sub routine a nd lo ad imm ediate d ata to ac c description the pr ogram cou nter is re stored fr om th e sta ck an d th e ac cumulator lo aded wit h th e sp ecifed immediate da ta. pr ogram ex ecution co ntinues at th e re stored ad dress. operation program c ounter st ack acc x affected fag(s) none reti return f rom in terrupt description the pro gram co unter i s res tored fro m th e st ack an d th e in terrupts are re- enabled by se tting th e emi bit . em i is th e ma ster in terrupt gl obal en able bit . if an in terrupt wa s pe nding wh en th e reti in struction i s ex ecuted, th e pe nding int errupt rou tine wi ll be pro cessed be fore ret urning to th e ma in pro gram. operation program c ounter st ack emi 1 affected fag(s) none rl [m] rotate da ta memor y le ft description the co ntents of th e sp ecifed da ta me mory ar e ro tated le ft by 1 bit wit h bit 7 ro tated in to bit 0. operation [m].(i+1) [m ].i; ( i=0~6) [m].0 [m] .7 affected fag(s) none rla [m] rotate data me mory l eft wi th res ult in ac c description the co ntents of th e sp ecifed da ta me mory ar e ro tated le ft by 1 bit wit h bit 7 ro tated in to bit 0. the ro tated re sult is sto red in th e ac cumulator an d th e co ntents of th e da ta me mory re main u ncha nged. operation acc.(i+1) [m ].i; ( i=0~6) acc.0 [m ].7 affected fag(s) none rlc [m] rotate data me mory le ft th rough c arry description the co ntents of th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated le ft by 1 bit . bit 7 replaces th e ca rry bit an d th e or iginal ca rry fag is ro tated in to bit 0. operation [m].(i+1) [m ].i; ( i=0~6) [m].0 c c [m] .7 affected fag(s) c rlca [m] rotate da ta me mory l eft th rough ca rry wi th res ult in ac c description data in th e sp ecifed da ta me mory a nd th e c arry fa g a re ro tated le ft by 1 bit . bit 7 re places th e carry bit an d th e or iginal ca rry fag is ro tated in to th e bit 0. the ro tated re sult is sto red in th e accumulator an d th e co ntents of th e da ta me mory re main un changed. operation acc.(i+1) [m ].i; ( i=0~6) acc.0 c c [m] .7 affected fag(s) c rr [m] rotate data memor y ri ght description the c ontents o f th e sp ecifed da ta me mory a re ro tated ri ght by 1 bit wit h bit 0 ro tated in to bit 7. operation [m].i [m ].(i+1); ( i=0~6) [m].7 [m] .0 affected fag(s) none
rev. 1.10 158 ?a? ?0? ?01? rev. 1.10 159 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? rra [m] rotate data me mory r ight w ith r esult in ac c description data in th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated ri ght by 1 bit wit h bit 0 rotated in to bit 7. the ro tated re sult is sto red in th e ac cumulator an d th e co ntents of th e data memor y rema in uncha nged. operation acc.i [m ].(i+1); ( i=0~6) acc.7 [m ].0 affected fag(s) none rrc [m] rotate data me mory ri ght th rough c arry description the co ntents of th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated ri ght by 1 bit . bit 0 replaces th e ca rry bit an d th e or iginal ca rry fag is ro tated in to bit 7. operation [m].i [m ].(i+1); ( i=0~6) [m].7 c c [m] .0 affected fag(s) c rrca [m] rotate da ta me mory r ight thr ough ca rry w ith r esult in ac c description data in th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated ri ght by 1 bit . bit 0 re places the ca rry bit an d th e or iginal ca rry fag is ro tated in to bit 7. the ro tated re sult is sto red in th e accumulator an d th e co ntents of th e da ta me mory re main un changed. operation acc.i [m ].(i+1); ( i=0~6) acc.7 c c [m] .0 affected fag(s) c sbc a,[m] subtract da ta memor y f rom ac c wit h ca rry description the co ntents of th e sp ecifed da ta me mory an d th e co mplement of th e ca rry fag ar e subtracted fro m th e ac cumulator. th e res ult i s st ored in th e ac cumulator. no te th at i f th e result of su btraction i s ne gative, th e c fa g wi ll be cl eared to 0, ot herwise i f th e res ult i s positive or ze ro, th e c fag wi ll be se t to 1. operation acc ac c ? [m ] ? c affected fag(s) ov, z, ac , c sbcm a,[m] subtract da ta memor y f rom ac c wit h ca rry and re sult in da ta memor y description the co ntents of th e sp ecifed da ta me mory an d th e co mplement of th e ca rry fag ar e subtracted fro m th e ac cumulator. th e res ult i s st ored in th e da ta me mory. no te th at i f th e result of su btraction i s ne gative, th e c fa g wi ll be cl eared to 0, ot herwise i f th e res ult i s positive or ze ro, th e c fag wi ll be se t to 1. operation [m] ac c ? [m] ? c affected fag(s) ov, z, ac , c sdz [m] skip if de crement da ta me mory is 0 description the co ntents of th e sp ecifed da ta me mory ar e frs t de cremented by 1. if th e re sult is 0 th e following in struction i s sk ipped. as th is req uires th e in sertion of a du mmy in struction wh ile the ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e pro gram proceeds wi th th e fo llowing in struction. operation [m] [m] ? 1 skip if [m ]=0 affected fag(s) none
rev. 1.10 160 ? a ? ? 0 ? ? 01 ? rev. 1.10 161 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? sdza [m] skip if de crement da ta me mory is zer o wit h re sult in ac c description the co ntents of th e sp ecifed da ta me mory ar e frs t de cremented by 1. if th e re sult is 0, th e following in struction i s sk ipped. th e res ult i s st ored in th e ac cumulator bu t th e spe cifed data me mory co ntents re main un changed. as th is re quires th e in sertion of a d ummy instruction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e re sult i s no t 0, the pro gram pro ceeds wi th th e fo llowing in struction. operation acc [m ] ? 1 skip if ac c=0 affected fag(s) none set [m] set da ta memor y description each bi t of th e sp ecifed da ta memor y is set to 1. operation [m] ff h affected fag(s) none set [m].i set bit of data memor y description bit i of th e sp ecifed da ta memor y is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment da ta memor y is 0 description the co ntents of th e spe cifed da ta me mory are fr st in cremented by 1. if th e res ult i s 0, th e following in struction i s sk ipped. as th is req uires th e in sertion of a du mmy in struction wh ile the ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e pro gram proceeds wi th th e fo llowing in struction. operation [m] [m] + 1 skip if [m ]=0 affected fag(s) none siza [m] skip i f in crement da ta me mory i s ze ro wi th res ult in ac c description the co ntents of th e spe cifed da ta me mory are fr st in cremented by 1. if th e res ult i s 0, th e following in struction i s sk ipped. th e res ult i s st ored in th e ac cumulator bu t th e spe cifed data me mory co ntents re main un changed. as th is re quires th e in sertion of a d ummy instruction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e pro gram pro ceeds wi th th e fo llowing in struction. operation acc [m ] + 1 skip if ac c=0 affected fag(s) none snz [m].i skip if bit i o f da ta me mory is no t 0 description if bi t i of th e spe cifed da ta me mory i s no t 0, th e fo llowing in struction i s sk ipped. as th is requires th e in sertion of a du mmy in struction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cycle in struction. if th e res ult i s 0 th e pro gram pro ceeds wi th th e fo llowing in struction. operation skip if [m ].i 0 affected fag(s) none sub a,[m] subtract da ta memor y f rom ac c description the sp ecifed da ta me mory is su btracted fr om th e co ntents of th e ac cumulator. the re sult is stored in th e ac cumulator. no te th at i f th e res ult of su btraction i s ne gative, th e c fa g wi ll be cleared to 0, ot herwise if th e re sult is po sitive or ze ro, th e c fag wi ll be se t to 1. operation acc ac c ? [m ] affected fag(s) ov, z, ac , c
rev. 1.10 160 ?a? ?0? ?01? rev. 1.10 161 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? subm a,[m] subtract da ta memor y f rom ac c wit h re sult in da ta memor y description the sp ecifed da ta me mory is su btracted fr om th e co ntents of th e ac cumulator. the re sult is stored in th e da ta me mory. no te th at i f th e res ult of su btraction i s ne gative, th e c fa g wi ll be cleared to 0, ot herwise if th e re sult is po sitive or ze ro, th e c fag wi ll be se t to 1. operation [m] ac c ? [m] affected fag(s) ov, z, ac , c sub a,x subtract immediate d ata fr om ac c description the imm ediate da ta sp ecifed by th e co de is su btracted fr om th e co ntents of th e ac cumulator. the res ult i s st ored in th e ac cumulator. no te th at i f th e res ult of su btraction i s ne gative, th e c fag wi ll be cl eared to 0, ot herwise if th e re sult is po sitive or ze ro, th e c fag wi ll be se t to 1. operation acc ac c ? x affected fag(s) ov, z, ac , c swap [m] swap nibbles o f da ta me mory description the lo w-order an d hi gh-order ni bbles of th e sp ecifed da ta me mory ar e in terchanged. operation [m].3~[m].0 ? [m] .7~[m].4 affected fag(s) none swapa [m] swap nib bles o f da ta me mory wit h re sult in ac c description the lo w-order an d hi gh-order ni bbles of th e sp ecifed da ta me mory ar e in terchanged. the result is sto red in th e ac cumulator. the co ntents of th e da ta me mory re main un changed. operation acc.3~acc.0 [m ].7~[m].4 acc.7~acc.4 [m ].3~[m].0 affected fag(s) none sz [m] skip if data me mory is 0 description if th e c ontents o f th e sp ecifed da ta me mory is 0 , th e f ollowing in struction is sk ipped. as thi s requires th e in sertion of a du mmy in struction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cycle in struction. if th e res ult i s no t 0 th e pro gram pro ceeds wi th th e fo llowing in struction. operation skip if [m ]=0 affected fag(s) none sza [m] skip if data me mory is 0 wit h d ata mo vement to ac c description the co ntents of th e sp ecifed da ta me mory ar e co pied to th e ac cumulator. if th e val ue is ze ro, the fo llowing in struction i s sk ipped. as th is req uires th e in sertion of a du mmy in struction while th e ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e program pro ceeds wi th th e fo llowing in struction. operation acc [m ] skip if [m ]=0 affected fag(s) none sz [m].i skip if bit i o f da ta me mory is 0 description if bi t i of th e spe cifed da ta me mory i s 0, th e fo llowing in struction i s sk ipped. as th is req uires the in sertion of a du mmy in struction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cy cle instruction. if th e res ult i s no t 0, th e pro gram pro ceeds wi th th e fo llowing in struction. operation skip if [m ].i=0 affected fag(s) none
rev. 1.10 16 ? ? a ? ? 0 ? ? 01 ? rev. 1.10 16? ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? tabrdc [m] read tab le (cu rrent pag e) to tb lh an d da ta me mory description the low by te of th e pro gram co de (c urrent pa ge) add ressed by th e ta ble po inter (t blp) i s moved to th e sp ecifed da ta memor y an d th e hi gh byt e mov ed to tb lh. operation [m] pro gram co de ( low byt e) tblh pro gram co de ( high byt e) affected fag(s) none tabrdl [m] read table ( last pa ge) to tb lh and da ta memor y description the low byt e of th e pro gram co de ( last pa ge) ad dressed by th e ta ble po inter ( tblp) is mov ed to th e sp ecifed da ta me mory an d th e hi gh by te mo ved to tb lh. operation [m] pro gram co de ( low byt e) tblh pro gram co de ( high byt e) affected fag(s) none xor a,[m] logical xo r da ta me mory to ac c description data in th e ac cumulator an d th e sp ecifed da ta me mory pe rform a bit wise lo gical xo r operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c xo r [m ] affected fag(s) z xorm a,[m] logical xo r ac c to da ta me mory description data in th e sp ecifed da ta me mory an d th e ac cumulator pe rform a bit wise lo gical xo r operation. th e res ult i s st ored in th e da ta me mory. operation [m] ac c x or [m] affected fag(s) z xor a,x logical xor imm ediate d ata to ac c description data in th e ac cumulator an d th e sp ecifed imm ediate da ta pe rform a bit wise lo gical xo r operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c xo r x affected fag(s) z
rev. 1.10 16? ?a? ?0? ?01? rev. 1.10 16 ? ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0. ?? 8 D 0. ? 44 b 0.150 D 0.157 c 0.01 ? D 0.0 ? 0 c ? 0. ? 86 D 0.40 ? d D D 0.069 e D 0.050 D f 0.004 D 0.010 g 0.016 D 0.050 h 0.007 D 0.010 0? D 8? symbol dimensions in mm min. nom. max. a 5.79 D 6. ? 0 b ? .81 D ? .99 c 0. ? 0 D 0.51 c ? 9.80 D 10. ? 1 d D D 1.75 e D 1. ? 7 D f 0.10 D 0. ? 5 g 0.41 D 1. ? 7 h 0.18 D 0. ? 5 0? D 8?
rev. 1.10 164 ? a ? ? 0 ? ? 01 ? rev. 1.10 165 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? 28-pin skdip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 1. ? 75 1. ? 95 b 0. ? 78 0. ? 98 c 0.1 ? 5 0.1 ? 5 d 0.1 ? 5 0.145 e 0.016 0.0 ? 0 f 0.050 0.070 g 100 h 0. ? 95 0. ? 15 i ? 75 symbol dimensions in mm min. nom. max. a ? 4.9 ? ? 5.4 ? b 7.06 7.57 c ? .18 ? .4 ? d ? .18 ? .68 e 0.41 0.51 f 1. ? 7 1.78 g ? .54 h 7.49 8.00 i 9.5 ?
rev. 1.10 164 ?a? ?0? ?01? rev. 1.10 165 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? 28-pin sop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 9 ? 0.419 b 0. ? 56 0. ? 00 c 0.01 ? 0.0 ? 0 c ? 0.697 0.71 ? d 0.104 e 0.050 f 4 0.01 ? g 16 0.050 h 8 0.01 ? 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.6 ? c 0. ? 0 0.51 c ? 17.70 18.11 d ? .64 e 1. ? 7 f 0.10 0. ? 0 g 0.41 1. ? 7 h 0. ? 0 0. ?? 0 8
rev. 1.10 166 ? a ? ? 0 ? ? 01 ? rev. 1.10 167 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.008 0.01 ? c ? 0. ? 86 0. ? 94 d 0.054 0.060 e 0.0 ? 5 f 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c ? 9.80 10.01 d 1. ? 7 1.5 ? e 0.64 f 0.10 0. ? 5 g 0.56 0.71 h 0.18 0. ? 5 0 8
rev. 1.10 166 ?a? ?0? ?01? rev. 1.10 167 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? 44-pin qfp (10mm10mm) outline dimensions symbol dimensions in mm min. nom. max. a 0.51 ? 0.5 ? 8 b 0. ? 90 0. ? 98 c 0.51 ? 0.5 ? 8 d 0. ? 90 0. ? 98 e 0.0 ? 1 f 0.01 ? g 0.075 0.087 h 0.106 i 0.010 0.0 ? 0 j 0.0 ? 9 0.0 ? 7 k 0.004 0.008 l 0.004 0 7 symbol dimensions in mm min. nom. max. a 1 ? .00 1 ? .40 b 9.90 10.10 c 1 ? .00 1 ? .40 d 9.90 10.10 e 0.8 f 0. ? g 1.90 ? . ? 0 h ? .70 i 0. ? 5 0.50 j 0.7 ? 0.9 ? k 0.10 0. ? 0 l 0.10 0 7
rev. 1.10 168 ? a ? ? 0 ? ? 01 ? rev. 1.10 169 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? reel dimensions 16-pin nsop(150mil) symbol description dimensions in mm a reel outer diameter ?? 0.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 1 ? .0 +0.5/-0. ? d ke ? slit width ? .00.5 t1 space between flang 16.8 +0. ? /-0. ? t ? reel thickness ?? . ? 0. ? sop 28w(300mil) symbol description dimensions in mm a reel outer diameter ?? 0.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 1 ? .0 +0.5/-0. ? d ke ? slit width ? .00.5 t1 space between flang ? 4.8 +0. ? /-0. ? t ? reel thickness ? 0. ? 0. ? ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter ?? 0.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 1 ? .0 +0.5/-0. ? d ke ? slit width ? .00.5 t1 space between flang 16.8 +0. ? /-0. ? t ? reel thickness ?? . ? 0. ?
rev. 1.10 168 ?a? ?0? ?01? rev. 1.10 169 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? carrier tape dimensions

16-pin nsop (150mil) symbol description dimensions in mm w carrier tape width 16.00. ? p cavit ? pitch 8.00.1 e perforation position 1.750.1 f cavit ? to perforation(width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavit ? hole diameter 1.50 +0. ? 5/-0.00 p0 perforation pitch 4.00.1 p1 cavit ? to perforation(length direction) ? .00.1 a0 cavit ? length 6.50.1 b0 cavit ? width 10. ? 0.1 k0 cavit ? depth ? .10.1 t carrier tape thickness 0. ? 00.05 c cover tape width 1 ? . ? 0.1
rev. 1.10 170 ? a ? ? 0 ? ? 01 ? rev. 1.10 171 ?a? ?0? ?01? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? sop 28w (300mil) symbol description dimensions in mm w carrier tape width ? 4.0+0. ? p cavit ? pitch 1 ? .00.1 e perforation position 1.750.10 f cavit ? to perforation(width direction) 11.50.1 d perforation diameter 1.5 +0.10/-0.0 d1 cavit ? hole diameter 1.50 +0. ? 5/-0.00 p0 perforation pitch 4.00.1 p1 cavit ? to perforation(length direction) ? .00.1 a0 cavit ? length 10.850.1 b0 cavit ? width ? .970.1 k0 cavit ? depth ? .970.10 t carrier tape thickness 0. ? 50.01 c cover tape width ? 1. ? 0.1 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.00. ? p cavit ? pitch 8.00.1 e perforation position 1.750.1 f cavit ? to perforation(width direction) 7.50.1 d perforation diameter 1.55 +0.1/-0.0 d1 cavit ? hole diameter 1.50 +0. ? 5/-0.00 p0 perforation pitch 4.00.1 p1 cavit ? to perforation(length direction) ? .00.1 a0 cavit ? length 6.50.1 b0 cavit ? width 10. ? 0.1 k0 cavit ? depth ? .10.1 t carrier tape thickness 0. ? 00.05 c cover tape width 1 ? . ? 0.1
rev. 1.10 170 ?a? ?0? ?01? rev. 1.10 171 ? a ? ? 0 ? ? 01 ? HT45FM2C brushless dc motor flash type 8-bit mcu HT45FM2C brushless dc motor flash type 8-bit mcu preliminar ? holtek semiconductor inc. (headquarters) no. ?? creation rd. ii ? science park ? hsinchu ? taiwan tel: 886- ? -56 ? -1999 fax: 886- ? -56 ? -1 189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f- ?? no. ? - ?? yuanqu st. ? nankang software park ? taipei 115 ? taiwan tel: 886- ? - ? 655-7070 fax: 886- ? - ? 655-7 ? 7 ? fax: 886- ? - ? 655-7 ? 8 ? (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit a ? productivit ? building ? no.5 gaoxin ? ? nd road ? nanshan district ? shenzhen ? china 518057 t el: 86-755-8616-9908 ? 86-755-8616-9 ? 08 fax: 86-755-8616-97 ?? holtek semiconductor (usa), inc. (north america sales offce) 467 ? 9 fremont blvd. ? fremont ? ca 945 ? 8 ? usa t el: 1-510- ? 5 ? -9880 fax: 1-510- ? 5 ? -9885 http://www .holtek.com cop ? right ? ? 01 ? b ? holtek se ? iconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however ? holt ek assumes no responsibilit ? ar ising from the use of the specifications described. the applications mentioned herein are used solel ? for the purpose of illustration and holtek makes no warrant ? or representation that such applications will be suitable without further modifcation, nor recommends the use of its products for application that ma ? present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or s ? stems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw .

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